17 Commits

Author	SHA1	Message	Date
Alex Forencich	b044ac10ff	Optimize offset_next computation ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2022-07-02 15:25:45 -07:00
Alex Forencich	93c2804b1b	Add pipeline register after barrel shift ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2022-07-02 15:24:28 -07:00
Alex Forencich	8797aa481f	Rework status FIFOs ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2022-07-02 15:24:05 -07:00
Alex Forencich	630648d5b0	Fix default parameter values ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2022-06-11 22:58:26 -07:00
Alex Forencich	70dc92c24e	Rework TLP interface parametrization ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2022-06-05 13:27:04 -07:00
Alex Forencich	dd7cc63d55	Correct reporting of request length statistics for zero-length operations in PCIe DMA IF modules	2022-03-31 17:04:03 -07:00
Alex Forencich	0b9c7671fb	Minor refactor of zero-length handling logic	2022-03-31 00:05:55 -07:00
Alex Forencich	c62df81292	Compute RAM_SEG_ADDR_WIDTH from RAM_ADDR_WIDTH	2022-02-15 00:39:46 -08:00
Alex Forencich	d2c72d3583	Add attributes to RAMs for proper synthesis in Quartus	2021-11-02 22:28:05 -07:00
Alex Forencich	f612d88288	Rewrite op tag FIFO read in DMA engines	2021-10-31 21:57:26 -07:00
Alex Forencich	90959b8795	Add default_nettype none and resetall directives	2021-10-20 17:49:30 -07:00
Alex Forencich	aee1431e74	Remove irrelevant address computation	2021-10-01 15:56:51 -07:00
Alex Forencich	1321e8e41a	Refactor check	2021-09-05 15:30:37 -07:00
Alex Forencich	8a6abc51ed	Add statistics outputs to DMA interface	2021-09-05 15:29:56 -07:00
Alex Forencich	6af4461705	Fix length register widths and max value handling	2021-08-20 16:09:58 -07:00
Alex Forencich	0563eb4727	Check MSBs	2021-08-20 14:12:26 -07:00
Alex Forencich	b95f030408	Add PCIe DMA interface modules and testbenches	2021-08-04 01:02:48 -07:00