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26 Commits

Author SHA1 Message Date
Alex Forencich
beaf1c6fbf fpga/mqnic/ZCU106/fpga_zynqmp: Add support for Ubuntu for ZCU106 MPSoC 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-02 01:53:24 -07:00
Alex Forencich
bb158d568f Add RX indirection table 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-10 15:05:32 -07:00
Alex Forencich
6c58e950d3 fpga/mqnic: Add DRAM interface module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-19 16:47:02 -08:00
Alex Forencich
aee97e4825 fpga/mqnic: Add performance-related MIG settings to config.tcl 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-17 23:16:19 -08:00
Alex Forencich
0644a12a48 fpga/mqnic: Remove extraneous top-level parameter RX_RSS_ENABLE from config.tcl scripts 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-03 21:32:51 -08:00
Alex Forencich
d3942da875 fpga: Add clock info register block 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-15 19:45:02 -07:00
Alex Forencich
01df80df86 fpga/mqnic: Disable MIGs by default 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-12 23:57:27 -07:00
Alex Forencich
5e52a52f5e fpga/mqnic: Add MIGs and HBM controllers for most boards 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-12 19:00:49 -07:00
Alex Forencich
d7904b8007 fpga: Add support for IRQ rate limiting 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-04 15:24:40 -07:00
Alex Forencich
1486da601f fpga: Add clock period parameters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-04 12:03:35 -07:00
Alex Forencich
5da044826d Add board-level configuration parameter for TDMA BER module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-18 11:25:58 -07:00
Alex Forencich
835f0d38f0 Update PTP subsystem to use separate clock for improved stability 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-06 17:46:16 -07:00
Alex Forencich
c2fea3a616 Add port register blocks with support for PHY link status reporting 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-04 09:03:37 -07:00
Alex Forencich
cfdd6f5455 Decouple transmit completion handling from PTP timestamping 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-01 17:41:47 -07:00
Alex Forencich
53f3547ef5 Rework hierarchy to move port-specific logic out of mqnic_core and into mqnic_interface and new port-level modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-29 14:32:57 -07:00
Alex Forencich
d5c2566dff Add statistics collection for AXI DMA IF 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-23 13:12:50 -07:00
Alex Forencich
2bd8350276 Add RX queue mapping module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-23 00:12:22 -07:00
Alex Forencich
7f8bbe30de Add application ID 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-21 13:15:45 -07:00
Alex Forencich
ba70498518 fpga: Add DMA immediate connections and parameters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-20 15:00:58 -07:00
Alex Forencich
f687aba432 fpga/mqnic: Update designs to use port mapping modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-13 01:37:10 -07:00
Alex Forencich
57905a5ef9 fpga/mqnic/ZCU106/fpga_zynqmp: Rewrite zynq PS TCL script, rework PS clock settings, switch to 300 MHz PL clock 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-11 12:25:51 -07:00
Alex Forencich
5f7c051b5b ZCU106/fpga_zynqmp: Sync module parameters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-07 21:41:06 -07:00
Joachim Foerster
80d5bda23f ZCU106/fpga_zynqmp: Fix maximum burst length for AXI Master 
Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
 2022-03-31 17:24:16 +02:00
Joachim Foerster
62879ff3ea ZCU106/fpga_zynqmp: Support parameter EVENT_QUEUE_INDEX_WIDTH, reduce Events queues to number of CPU cores 
- Keep parameter defaults in Verilog file at global of 32, though
- Select 4 Event queues via config.tcl, only

Signed-off-by: Andreas Braun <andreas.braun@missinglinkelectronics.com>
Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
 2022-03-31 17:24:16 +02:00
Andreas Braun
dce11522fa ZCU106/fpga_zynqmp: Reduce number of RX/TX queues to 32 
Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
 2022-03-31 17:22:27 +02:00
Andreas Braun
35517037e6 ZCU106/: Add design based on ZynqMP PS as host system, Vivado v2021.1 
Signed-off-by: Andreas Braun <andreas.braun@missinglinkelectronics.com>
Signed-off-by: Joachim Förster <joachim.foerster@missinglinkelectronics.com>
 2022-03-31 17:22:27 +02:00