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Commit Graph

64 Commits

Author SHA1 Message Date
Alex Forencich
463f2053b0 Add port register port_mtu 2019-11-18 16:30:32 -08:00
Alex Forencich
489506e4c0 Add FPGA ID register 2019-11-17 12:46:27 -08:00
Alex Forencich
f53a6b20e8 Add timeslot count to port registers 2019-11-05 16:59:40 -08:00
Alex Forencich
fa5e013255 Add MQNIC_MAX_SCHED define 2019-11-05 16:45:58 -08:00
Alex Forencich
e92485a41e Fix register definitions 2019-11-05 16:44:57 -08:00
Alex Forencich
f43cd09dac Add ExaNIC X25 mqnic design 2019-10-30 17:43:33 -07:00
Alex Forencich
d977cbdac2 Add feature bits 2019-08-19 23:43:52 -07:00
Alex Forencich
5f066b9fcd Adjust ExaNIC board ID to match original PCIe ID 2019-08-19 22:04:10 -07:00
Alex Forencich
d8a2efc756 Add port management code to driver 2019-08-19 15:59:57 -07:00
Alex Forencich
d99f40db08 Add port CSRs 2019-08-13 00:27:09 -07:00
Alex Forencich
5c736fc094 More hardware IDs 2019-07-23 22:30:26 -07:00
Alex Forencich
762037e8a8 Updates to be able to share header with userspace code 2019-07-21 21:51:14 -07:00
Alex Forencich
a6c4b8b1b7 Change board IDs 2019-07-21 15:27:01 -07:00
Alex Forencich
6c5b6c99a1 Initial commit of mqnic kernel module 2019-07-17 18:13:51 -07:00