Alex Forencich
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3d06b34679
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fpga: Add DRAM bandwidth test to DMA benchmark application
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-03-29 14:27:46 -07:00 |
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Alex Forencich
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d6bac395f3
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fpga/app/dma_bench: Add DRAM test channel module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-03-29 14:23:52 -07:00 |
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Alex Forencich
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bee1703199
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fpga/app/dma_bench: Refactor DMA benchmark application, use register blocks
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-11-30 23:26:05 -08:00 |
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Alex Forencich
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941288e926
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fpga/common: Add AXI interfaces for DDR and HBM to core logic and application section
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-10-12 17:12:23 -07:00 |
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Alex Forencich
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1486da601f
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fpga: Add clock period parameters
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-09-04 12:03:35 -07:00 |
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Alex Forencich
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ef5b2449dc
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Add stretched PTP PPS output
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-07-18 22:25:58 -07:00 |
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Alex Forencich
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835f0d38f0
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Update PTP subsystem to use separate clock for improved stability
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-05-06 17:46:16 -07:00 |
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Alex Forencich
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cfdd6f5455
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Decouple transmit completion handling from PTP timestamping
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-05-01 17:41:47 -07:00 |
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Alex Forencich
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d45857fb98
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fpga/app/dma_bench: Add DMA benchmark application
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-04-21 14:19:43 -07:00 |
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