64 Commits

Author	SHA1	Message	Date
Alex Forencich	bf3143a79f	Fix test name	2021-08-03 01:54:00 -07:00
Alex Forencich	ee9c719bf4	Add error reporting to DMA modules	2021-08-01 10:59:38 -07:00
Alex Forencich	51caad0810	Extract port counts	2021-06-01 13:22:48 -07:00
Alex Forencich	a45c36e802	Update testbenches	2021-04-12 22:55:38 -07:00
Alex Forencich	bf2a779e48	Rewrite test	2021-03-24 22:00:20 -07:00
Alex Forencich	bb30f0a50f	Extract parameter values from cocotb.top	2021-03-22 18:07:04 -07:00
Alex Forencich	be689ebb77	Update testbenches	2021-03-06 19:55:50 -08:00
Alex Forencich	03a78413c5	Rework sim_build output directory, fix default makefile target	2020-12-29 16:09:02 -08:00
Alex Forencich	3a59569105	Remove extraneous import	2020-12-28 18:53:00 -08:00
Alex Forencich	db58c836f6	Use absolute path to test directory	2020-12-28 18:52:47 -08:00
Alex Forencich	9ab1fb44b1	Convert send/recv to blocking	2020-12-18 16:50:50 -08:00
Alex Forencich	ca7f0131ea	Remove unnecessary __init__.py files	2020-12-15 18:59:49 -08:00
Alex Forencich	de53699ed4	Add top-level makefile	2020-12-04 15:41:10 -08:00
Alex Forencich	72f5a2d1cb	Add cocotb testbenches	2020-12-04 15:32:14 -08:00
Alex Forencich	21dbe318b4	Add AXI lite clock domain crossing module, testbench, and timing constraints	2019-07-09 00:18:27 -07:00
Alex Forencich	ed344f352f	Add AXI to AXI lite adapter modules and testbenches	2019-07-08 17:51:12 -07:00
Alex Forencich	7b713199ad	Add AXI nonblocking crossbar interconnect module and testbench	2019-02-25 18:37:46 -08:00
Alex Forencich	57dd292ae9	Add AXI RAM interface modules, AXI dual port RAM module, and testbench	2019-02-01 18:22:03 -08:00
Alex Forencich	199a5544ca	Use correct wait	2019-02-01 17:28:22 -08:00
Alex Forencich	787f198970	Add AXI lite dual-port RAM module and testbench	2019-01-17 17:48:23 -08:00
Alex Forencich	818fac5daa	Update signal names	2019-01-16 19:37:15 -08:00
Alex Forencich	523bf689d8	Add optional output pipeline register to AXI lite RAM	2019-01-09 00:25:40 -08:00
Alex Forencich	513a53e52d	Add AXI DMA module and testbench	2018-12-27 14:21:06 -08:00
Alex Forencich	41f8667310	Add AXI write DMA module and testbenches	2018-12-27 14:15:51 -08:00
Alex Forencich	21ed77e4c0	Add AXI stream endpoint module	2018-12-27 13:49:48 -08:00
Alex Forencich	76fba3ac84	Add AXI central DMA module and testbenches	2018-12-06 17:27:44 -08:00
Alex Forencich	3587cf5285	Fix AXI memory model bug	2018-12-06 15:14:54 -08:00
Alex Forencich	43234018cd	Add AXI read DMA module and testbenches	2018-12-03 23:29:22 -08:00
Alex Forencich	61df54e62d	Add M_REGIONS and M_SECURE parameters, add address range overlap check	2018-12-03 13:17:45 -08:00
Alex Forencich	7141a75ce8	Remove region inputs	2018-12-03 13:15:55 -08:00
Alex Forencich	0dbf0b1cff	Add optional output pipeline register to AXI RAM module	2018-11-27 01:17:31 -08:00
Alex Forencich	a25c4b17eb	Add AXI shared interconnect and testbench	2018-08-22 23:42:31 -07:00
Alex Forencich	82a13479e7	Add decode error tests	2018-08-22 20:43:28 -07:00
Alex Forencich	e696abbdff	Add AXI lite shared interconnect module and testbench	2018-08-22 20:34:31 -07:00
Alex Forencich	2a4c63e859	Change default address width to 32	2018-08-21 22:38:32 -07:00
Alex Forencich	7c40254d7e	Remove redundant testbenches	2018-08-21 22:27:47 -07:00
Alex Forencich	6a002e2ce0	Add CONVERT_NARROW_BURST and FORWARD_ID parameters to AXI adapter	2018-08-20 23:23:00 -07:00
Alex Forencich	b15e8d9f63	Add AXI adapters and testbenchs	2018-08-20 19:10:08 -07:00
Alex Forencich	160f20bc8c	Change default awcache/arcache value	2018-08-17 16:29:12 -07:00
Alex Forencich	e06d607b85	Add AXI lite width adapter and testbenches	2018-08-16 16:37:11 -07:00
Alex Forencich	48577f3a2d	Add simple register as a per-channel option to AXI register modules	2018-08-16 13:25:07 -07:00
Alex Forencich	d541c64bc0	Add AXI lite registers and testbenches	2018-08-16 13:01:45 -07:00
Alex Forencich	97cbbd1781	Don't crash when omitting read or write port connections	2018-08-16 12:50:14 -07:00
Alex Forencich	4adcf9c7d0	Add prot and resp signal encoding constants	2018-08-15 23:02:57 -07:00
Alex Forencich	ad453b12db	Add AXI lite RAM module and testbench	2018-08-14 23:49:40 -07:00
Alex Forencich	57abfa66bc	Add MyHDL AXI4 Lite master model, RAM model, and testbench	2018-08-14 23:49:11 -07:00
Alex Forencich	b8e6b30717	Don't use narrow bursts for setup and checking in AXI RAM testbench	2018-08-14 23:44:15 -07:00
Alex Forencich	5614f7dafe	When pausing the AXI model, do not drop valid signals if they are asserted and waiting for a ready signal assert	2018-08-14 23:38:08 -07:00
Alex Forencich	09759518fc	ID always zero if ID pins not connected	2018-08-14 21:48:24 -07:00
Alex Forencich	649179894a	Remove unnecessary asserts	2018-08-14 21:46:05 -07:00