3238 Commits

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Author	SHA1	Message	Date
Alex Forencich	54bfdaa8c0	Cast WL to int	2015-03-21 03:19:43 -07:00
Alex Forencich	4981d7cacd	Update MyHDL repo	2015-03-21 02:56:17 -07:00
Alex Forencich	3138795899	Fix rate limiter testbenches	2015-03-21 02:55:30 -07:00
Alex Forencich	51b5335318	Remove z from default states for FSM inference	2015-03-09 02:38:39 -07:00
Alex Forencich	d73b296903	Properly handle short packets	2015-03-04 13:06:29 -08:00
Alex Forencich	8ba6cf00d6	Test very short packets	2015-03-04 12:58:22 -08:00
Alex Forencich	17ad08e412	Add 64-bit Ethernet FCS inserter	2015-03-04 00:33:26 -08:00
Alex Forencich	263891b3f6	Make sure all paths set state_next	2015-03-04 00:31:41 -08:00
Alex Forencich	47a3a50b65	Move preamble out of gmii endpoint	2015-03-03 23:47:27 -08:00
Alex Forencich	23fa1f1207	Handle tlast on first cycle	2015-03-03 21:46:02 -08:00
Alex Forencich	43999fb360	Add testbench for FCS insert with padding	2015-03-03 00:46:53 -08:00
Alex Forencich	ff14639eea	Test FCS inserter with padding insertion enabled	2015-02-28 23:13:02 -08:00
Alex Forencich	d3e30d0a73	Fix padding bug	2015-02-28 23:09:41 -08:00
Alex Forencich	08dd43defc	Add frame length asserts to gigabit MAC testbench	2015-02-28 23:08:53 -08:00
Alex Forencich	d489468776	Add example design for Digilent Atlys board	2015-02-28 20:05:05 -08:00
Alex Forencich	5a5c78be64	merged changes in axis	2015-02-28 19:32:38 -08:00
Alex Forencich	6e2eda256d	Improve frame drop logic in frame FIFOs, add DROP_WHEN_FULL option to disable input tready signal	2015-02-28 19:32:08 -08:00
Alex Forencich	14e71d568d	Improve classifier logic by registering payload select signals	2015-02-28 19:14:22 -08:00
Alex Forencich	d57c857d88	Put PHY interface registers into IOBs for timing	2015-02-28 18:24:20 -08:00
Alex Forencich	7532915bb7	Add GMII PHY interface module	2015-02-28 01:11:03 -08:00
Alex Forencich	6b4dd02946	Resolve multiple driver issue	2015-02-28 00:43:27 -08:00
Alex Forencich	3ef81acbb7	Update readme	2015-02-26 23:09:37 -08:00
Alex Forencich	1ec5012cd8	Update readme	2015-02-26 22:57:39 -08:00
Alex Forencich	b892fd1172	Add UDP complete module and testbench	2015-02-26 22:57:24 -08:00
Alex Forencich	635f05e9c6	Remove udp_ip_protocol input	2015-02-26 22:37:40 -08:00
Alex Forencich	27f319b91e	Fix UDP EP parse_eth	2015-02-26 22:36:05 -08:00
Alex Forencich	10108d5d1a	Add 2 port IP mux components	2015-02-26 22:05:07 -08:00
Alex Forencich	b2ea1c8568	Add parameters to ip_complete testbenches	2015-02-26 21:41:51 -08:00
Alex Forencich	d34aaf784d	Add UDP modules	2015-02-26 21:19:26 -08:00
Alex Forencich	ca94f1ded9	Update readme	2015-02-26 19:17:34 -08:00
Alex Forencich	b10beab08f	Update readme	2015-02-26 19:16:17 -08:00
Alex Forencich	6dee616834	Add gigabit MAC module	2015-02-26 19:16:08 -08:00
Alex Forencich	bb31d57921	Add GMII endpoint module	2015-02-26 19:15:31 -08:00
Alex Forencich	218d3f1b0f	Add assert for error_bad_fcs signal	2015-02-26 19:05:56 -08:00
Alex Forencich	bfe6c37ca9	Add ethernet FCS inserter and checker	2015-02-26 19:00:33 -08:00
Alex Forencich	bf847ff540	Update readme	2015-02-26 16:14:09 -08:00
Alex Forencich	da04654196	Add Ethernet FCS calculator modules	2015-02-26 16:11:04 -08:00
Alex Forencich	43fe36087c	Update readme	2015-02-26 16:04:57 -08:00
Alex Forencich	9265ab0946	Properly handle eth_fcs of None	2015-02-26 15:58:20 -08:00
Alex Forencich	c25c35d198	Add Ethernet CRC modules	2015-02-25 14:40:26 -08:00
Alex Forencich	f3ea7cd8ac	Add FCS field to eth_ep	2015-02-24 20:26:24 -08:00
Alex Forencich	7775733120	merged changes in axis	2014-12-03 21:48:34 -08:00
Alex Forencich	8582ab0749	Update readme	2014-12-03 19:00:12 -08:00
Alex Forencich	3c7e3b0424	Add SRL register module and testbench	2014-12-03 18:51:46 -08:00
Alex Forencich	10fd51f192	Add SRL FIFO module and testbench	2014-12-03 18:49:33 -08:00
Alex Forencich	385e358c08	Use non-broken myhdl	2014-12-03 18:02:53 -08:00
Alex Forencich	a545ed5170	merged changes in axis	2014-12-03 13:55:08 -08:00
Alex Forencich	b83dd34185	Fix register names	2014-12-03 13:15:13 -08:00
Alex Forencich	51a3f77283	merged changes in axis	2014-11-21 10:43:52 -08:00
Alex Forencich	fbcbbe3a69	Remove adder tree	2014-11-21 10:43:20 -08:00