110 Commits

Author	SHA1	Message	Date
Alex Forencich	f92c1ea980	Reorder capability registrations	2019-02-28 23:46:39 -08:00
Alex Forencich	1480be2173	Rewrite capability management	2019-02-28 23:45:23 -08:00
Alex Forencich	6baede4717	Broadcast message support	2019-02-15 18:04:46 -08:00
Alex Forencich	1630200cd8	Implement proper downstream TLP routing	2019-02-15 17:55:24 -08:00
Alex Forencich	178133498b	Fix indentation	2019-02-15 17:23:33 -08:00
Alex Forencich	13d35569fa	Match IO bars for routing IO operations	2019-02-15 17:23:14 -08:00
Alex Forencich	35a4d62fb8	Split SwitchBridge into separate upstream and downstream ports	2019-02-15 16:56:21 -08:00
Alex Forencich	247bca01f3	Add default_switch_port parameter	2019-02-15 15:26:09 -08:00
Alex Forencich	8cb607be04	Fix calls to read and write root complex regions	2019-02-15 14:40:24 -08:00
Alex Forencich	9f36acebc2	Print TLP payloads in hex	2019-01-28 18:17:21 -08:00
Alex Forencich	667b5c42c5	Add support for registering MSI callbacks	2019-01-28 16:30:19 -08:00
Alex Forencich	bb4fa0bfa0	Update testbenches	2019-01-02 02:00:46 -08:00
Alex Forencich	28fa143ae5	Add Ultrascale PCIe DMA modules and testbenches	2018-11-26 23:23:54 -08:00
Alex Forencich	008a7167c7	Add AXI_MAX_BURST_SIZE parameter to PCIe AXI master	2018-11-26 18:03:54 -08:00
Alex Forencich	6e46c8e32d	Add PCIe tag manager	2018-10-29 17:54:10 -07:00
Alex Forencich	e0b2416100	Add AXI model	2018-10-23 22:39:12 -07:00
Alex Forencich	4c9c493aa4	Add Ultrascale PCIe AXI master module and testbenches	2018-10-23 22:28:06 -07:00
Alex Forencich	d34a3e881e	Add Ultrascale PCIe AXI master write module and testbenches	2018-10-23 22:26:04 -07:00
Alex Forencich	5a02ba2cb1	Use yield from more consistently	2018-10-23 21:24:39 -07:00
Alex Forencich	b3ebb04491	Add Ultrascale PCIe AXI master read module and testbenches	2018-10-23 20:50:48 -07:00
Alex Forencich	ab82ea5296	Match IP core ordering	2018-10-16 18:02:28 -07:00
Alex Forencich	6f9c2a1ed2	Add MSI support to Ultrascale PCIe model	2018-10-15 14:18:27 -07:00
Alex Forencich	35ccc2ffd5	Add pause signals	2018-10-15 14:17:00 -07:00
Alex Forencich	4adaa480ca	Mask out old field value	2018-10-15 13:52:05 -07:00
Alex Forencich	22850707a6	Address is relative to beginning of region	2018-10-15 13:51:43 -07:00
Alex Forencich	be8ef351ce	Fix off-by-one error	2018-10-15 13:51:19 -07:00
Alex Forencich	8ada97200f	Update signal widths	2018-10-15 13:41:29 -07:00
Alex Forencich	325df5152f	Don't reimplement mem_write for MSI and MSI-X	2018-10-15 11:39:33 -07:00
Alex Forencich	15fdbfeba7	Add attr and tc parameters to mem_read and mem_write	2018-10-15 11:35:37 -07:00
Alex Forencich	e19c84c092	Add msi_register_signal	2018-10-15 10:37:35 -07:00
Alex Forencich	bafae02651	Add MSI test	2018-10-15 00:10:39 -07:00
Alex Forencich	997db1e141	Implment MSI support in RootComplex	2018-10-15 00:08:22 -07:00
Alex Forencich	80c8e01bfd	Add issue_msi_interrupt and issue_msix_interrupt	2018-10-15 00:07:40 -07:00
Alex Forencich	45f3614afb	Add MSI_CAP_LEN and MSIX_CAP_LEN	2018-10-15 00:06:57 -07:00
Alex Forencich	76dccafe0e	Consolidate MSI capability objects	2018-10-15 00:05:37 -07:00
Alex Forencich	2b9e4ccb78	Add get_capability_offset to TreeItem	2018-10-15 00:00:13 -07:00
Alex Forencich	cbd1577129	yield config_read and config_write	2018-10-14 23:59:03 -07:00
Alex Forencich	9f4e62333a	Rename parameter to dev	2018-10-14 23:57:53 -07:00
Alex Forencich	6a02c753e9	Incrementally build tree	2018-10-14 23:43:04 -07:00
Alex Forencich	a4e2a65902	Memory writes don't get assigned tags	2018-10-14 20:30:44 -07:00
Alex Forencich	0e601554cb	Set address in set_be and set_be_data	2018-10-14 20:29:34 -07:00
Alex Forencich	c047716ae8	The only locked completions are for locked memory reads	2018-10-06 17:28:21 -07:00
Alex Forencich	2059e3b16f	Generate is_eof_0	2018-10-06 17:27:16 -07:00
Alex Forencich	a2a43dd11d	Fix parity polarity	2018-10-06 17:00:51 -07:00
Alex Forencich	0928bf80bb	Fix sign error	2018-10-02 00:26:37 -07:00
Alex Forencich	c4da967da9	Correct lower address	2018-10-01 18:08:56 -07:00
Alex Forencich	51019f0d62	Fix read TLP handling	2018-10-01 17:47:05 -07:00
Alex Forencich	00515d4342	TLP validation asserts	2018-10-01 16:16:26 -07:00
Alex Forencich	2fef5c51df	Add PcieId object	2018-10-01 15:41:00 -07:00
Alex Forencich	4eb0ab240d	Add fmt_type property to TLP	2018-09-30 19:14:19 -07:00