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Author SHA1 Message Date
Alex Forencich
e882ed143f Update example designs 2018-11-08 09:20:33 -08:00
Alex Forencich
0a6bee6d69 Update example designs 2018-11-08 09:17:29 -08:00
Alex Forencich
29eccbc290 Update readme 2018-11-07 23:26:11 -08:00
Alex Forencich
6b1b36ded6 Assert header ready earlier if possible 2018-11-07 23:10:07 -08:00
Alex Forencich
b223c94adb Use registered header 2018-11-07 23:08:40 -08:00
Alex Forencich
d2fedc4134 Rename ports 2018-11-07 22:35:06 -08:00
Alex Forencich
b3f50ac2c7 Fix comments 2018-11-02 00:40:15 -07:00
Alex Forencich
98fc042489 Convert generated udp_demux to verilog parametrized module 2018-11-02 00:39:52 -07:00
Alex Forencich
81e9aa0c77 Convert generated ip_demux to verilog parametrized module 2018-11-02 00:25:23 -07:00
Alex Forencich
18c4214edb Convert generated eth_demux to verilog parametrized module 2018-11-02 00:23:31 -07:00
Alex Forencich
470ab887d9 Update mux instances 2018-11-01 00:59:14 -07:00
Alex Forencich
fea1186f57 Convert generated udp_arb_mux to verilog parametrized module 2018-11-01 00:48:26 -07:00
Alex Forencich
554e0a5380 Convert generated ip_arb_mux to verilog parametrized module 2018-11-01 00:40:09 -07:00
Alex Forencich
96cefbe0c1 Convert generated eth_arb_mux to verilog parametrized module 2018-10-31 21:42:28 -07:00
Alex Forencich
67025121ab Convert generated udp_mux to verilog parametrized module 2018-10-31 18:09:44 -07:00
Alex Forencich
f20312b199 Convert generated ip_mux to verilog parametrized module 2018-10-31 18:08:39 -07:00
Alex Forencich
d28d459d70 Convert generated eth_mux to verilog parametrized module 2018-10-31 15:48:12 -07:00
Alex Forencich
68abccd0a1 Workaround for MyHDL race condition 2018-10-31 13:42:33 -07:00
Alex Forencich
c08026277e Fix source pause logic 2018-10-31 13:42:08 -07:00
Alex Forencich
7d6889add6 Update example designs 2018-10-30 21:32:32 -07:00
Alex Forencich
6ffdc5f53d merged changes in axis 2018-10-30 17:36:40 -07:00
Alex Forencich
8d564b1074 Convert localparam to parameter as Vivado does not like clog2 in localparams 2018-10-30 17:35:38 -07:00
Alex Forencich
733044b0df Work around MyHDL sync race condition 2018-10-30 11:59:09 -07:00
Alex Forencich
20017c04b9 Work around MyHDL cosimulation race condition 2018-10-30 11:58:53 -07:00
Alex Forencich
ad8828d5b7 Update FIFO instances 2018-10-30 11:58:06 -07:00
Alex Forencich
e89097c8b1 merged changes in axis 2018-10-25 16:07:04 -07:00
Alex Forencich
be51f2b472 Update FIFO instantiations 2018-10-25 16:06:32 -07:00
Alex Forencich
ded363b471 Rename status outputs 2018-10-25 15:36:34 -07:00
Alex Forencich
ebe9d17bd5 Update readme 2018-10-25 14:30:42 -07:00
Alex Forencich
ed4a2d73c2 Add axis_pipeline_register module 2018-10-25 14:29:35 -07:00
Alex Forencich
ceedd0f8f5 Update readme 2018-10-25 14:27:24 -07:00
Alex Forencich
312d90addb Add wrapper generators 2018-10-25 14:23:00 -07:00
Alex Forencich
49d415d59f Disable dump file output under travis-ci 2018-10-25 12:14:12 -07:00
Alex Forencich
e9d9f32150 Rename ports 2018-10-25 12:00:34 -07:00
Alex Forencich
6f4ab8f180 Rename ports 2018-10-25 11:59:13 -07:00
Alex Forencich
84a758f100 Rename ports 2018-10-25 11:56:52 -07:00
Alex Forencich
6c1ea89a66 Rename ports 2018-10-25 11:52:08 -07:00
Alex Forencich
fd28040c40 Rename ports 2018-10-25 11:30:35 -07:00
Alex Forencich
7997a4a844 Rename ports 2018-10-25 11:19:28 -07:00
Alex Forencich
8d9da455cd Minor optimizations 2018-10-25 10:29:31 -07:00
Alex Forencich
e926daabaf Update readme 2018-10-25 10:24:42 -07:00
Alex Forencich
cb9f2132a4 Update parameter ordering 2018-10-25 10:20:17 -07:00
Alex Forencich
09a8fa51b6 Rename ports 2018-10-25 10:19:32 -07:00
Alex Forencich
c47f3ea03d Update FIFO instance, rename ports 2018-10-25 10:17:58 -07:00
Alex Forencich
d1ed1528b5 Update FIFO instance, rename ports 2018-10-25 10:15:16 -07:00
Alex Forencich
11d9dbe24a Merge axis_async_fifo and axis_async_frame_fifo, rename ports 2018-10-25 09:53:38 -07:00
Alex Forencich
36d0a8786f Merge axis_fifo and axis_frame_fifo, rename ports 2018-10-24 23:16:06 -07:00
Alex Forencich
3d2efef93a Update readme 2018-10-24 22:25:02 -07:00
Alex Forencich
2bb9f11c9e Use logical operators 2018-10-24 22:24:27 -07:00
Alex Forencich
3bbf8524d6 Compute DEST_WIDTH 2018-10-24 22:21:31 -07:00