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Author SHA1 Message Date
Alex Forencich
a2a43dd11d Fix parity polarity 2018-10-06 17:00:51 -07:00
Alex Forencich
0928bf80bb Fix sign error 2018-10-02 00:26:37 -07:00
Alex Forencich
c4da967da9 Correct lower address 2018-10-01 18:08:56 -07:00
Alex Forencich
51019f0d62 Fix read TLP handling 2018-10-01 17:47:05 -07:00
Alex Forencich
00515d4342 TLP validation asserts 2018-10-01 16:16:26 -07:00
Alex Forencich
2fef5c51df Add PcieId object 2018-10-01 15:41:00 -07:00
Alex Forencich
4eb0ab240d Add fmt_type property to TLP 2018-09-30 19:14:19 -07:00
Alex Forencich
32893353d3 Improve TLP packer and unpacker error handling 2018-09-28 16:49:49 -07:00
Alex Forencich
5acd5f06fb Handle maximum length and byte count values 2018-09-28 16:48:40 -07:00
Alex Forencich
1f968f1aea Add get_id to Function, use set_completion_data 2018-09-28 16:42:17 -07:00
Alex Forencich
7c184bee59 Generate last byte enable offset correctly for single DWORD operations 2018-09-28 16:39:53 -07:00
Alex Forencich
2f279b55b3 Add has_data and status parameters to set_completion, add set_completion_data 2018-09-28 16:36:46 -07:00
Alex Forencich
16fdbba010 Fix RC packer bug 2018-09-28 01:06:36 -07:00
Alex Forencich
b5cfb9d025 Handshaking fixes 2018-09-26 20:11:25 -07:00
Alex Forencich
0bcd30501f More tests and asserts 2018-09-26 20:10:56 -07:00
Alex Forencich
c25a13041e Add Ultascale PCIe AXI lite master module and testbenches 2018-09-25 21:09:20 -07:00
Alex Forencich
f7947d883a Add AXI stream endpoint model 2018-09-25 20:55:44 -07:00
Alex Forencich
c57ef057ee Initial commit 2018-09-25 19:50:57 -07:00
Alex Forencich
553547f661 Fix test naming 2018-09-09 13:52:13 -07:00
Alex Forencich
b289e02fe4 Remove extraneous code 2018-08-26 14:06:57 -07:00
Alex Forencich
71427e7cf0 Update default parameters 2018-08-26 14:05:10 -07:00
Alex Forencich
07a4da3bea Fix connect logic 2018-08-23 16:20:58 -07:00
Alex Forencich
4f01dfb7d5 Support single slave interface 2018-08-23 14:43:57 -07:00
Alex Forencich
f1fb5b368c Fix connect logic 2018-08-23 14:41:40 -07:00
Alex Forencich
a25c4b17eb Add AXI shared interconnect and testbench 2018-08-22 23:42:31 -07:00
Alex Forencich
1753a2e6cf Remove extraneous logic 2018-08-22 22:28:15 -07:00
Alex Forencich
8427aa12bf Simplify request logic 2018-08-22 22:27:52 -07:00
Alex Forencich
fe7396a31e Update readme 2018-08-22 21:55:08 -07:00
Alex Forencich
0e36f647cb Add arbiter and priority encoder modules 2018-08-22 21:50:31 -07:00
Alex Forencich
82a13479e7 Add decode error tests 2018-08-22 20:43:28 -07:00
Alex Forencich
e696abbdff Add AXI lite shared interconnect module and testbench 2018-08-22 20:34:31 -07:00
Alex Forencich
2a4c63e859 Change default address width to 32 2018-08-21 22:38:32 -07:00
Alex Forencich
7c40254d7e Remove redundant testbenches 2018-08-21 22:27:47 -07:00
Alex Forencich
6a002e2ce0 Add CONVERT_NARROW_BURST and FORWARD_ID parameters to AXI adapter 2018-08-20 23:23:00 -07:00
Alex Forencich
b15e8d9f63 Add AXI adapters and testbenchs 2018-08-20 19:10:08 -07:00
Alex Forencich
160f20bc8c Change default awcache/arcache value 2018-08-17 16:29:12 -07:00
Alex Forencich
e06d607b85 Add AXI lite width adapter and testbenches 2018-08-16 16:37:11 -07:00
Alex Forencich
48577f3a2d Add simple register as a per-channel option to AXI register modules 2018-08-16 13:25:07 -07:00
Alex Forencich
d541c64bc0 Add AXI lite registers and testbenches 2018-08-16 13:01:45 -07:00
Alex Forencich
97cbbd1781 Don't crash when omitting read or write port connections 2018-08-16 12:50:14 -07:00
Alex Forencich
4adcf9c7d0 Add prot and resp signal encoding constants 2018-08-15 23:02:57 -07:00
Alex Forencich
becfbf4425 When pausing the AXI stream model, do not drop tvalid if it is asserted and waiting for tready to be asserted 2018-08-15 00:11:39 -07:00
Alex Forencich
ad453b12db Add AXI lite RAM module and testbench 2018-08-14 23:49:40 -07:00
Alex Forencich
57abfa66bc Add MyHDL AXI4 Lite master model, RAM model, and testbench 2018-08-14 23:49:11 -07:00
Alex Forencich
b8e6b30717 Don't use narrow bursts for setup and checking in AXI RAM testbench 2018-08-14 23:44:15 -07:00
Alex Forencich
5614f7dafe When pausing the AXI model, do not drop valid signals if they are asserted and waiting for a ready signal assert 2018-08-14 23:38:08 -07:00
Alex Forencich
09759518fc ID always zero if ID pins not connected 2018-08-14 21:48:24 -07:00
Alex Forencich
649179894a Remove unnecessary asserts 2018-08-14 21:46:05 -07:00
Alex Forencich
2113bb1795 Add AXI registers and testbenches 2018-08-13 23:36:47 -07:00
Alex Forencich
5f302d8106 Fix some more issues in AXI RAM module 2018-08-13 16:00:29 -07:00