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Author SHA1 Message Date
Alex Forencich
338457cd75 merged changes in pcie 2022-08-15 23:47:49 -07:00
Alex Forencich
a2f07db39f Remove redundant abort signal connection 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-14 14:55:01 -07:00
Alex Forencich
60dd672f6d Move pause signal connection to improve timing 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-14 14:54:27 -07:00
Alex Forencich
edf9b260ab Rename module to match file name 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-14 14:53:15 -07:00
Alex Forencich
4d303ba11b meta-corundum/recipes-devtools/mqnic-tools: Add missing symlink 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-12 13:34:27 -07:00
Alex Forencich
1c1db788ac fpga/common: Fix incorrect parameters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-08 13:10:05 -07:00
Alex Forencich
693809ab97 modules/mqnic: Use DMA_TO/FROM_DEVICE macros instead of the PCI versions 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-06 01:27:19 -07:00
Alex Forencich
d0ce01de7f fpga/mqnic/S10DX_DK: fix typo 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-05 16:28:15 -07:00
Alex Forencich
6c6648f114 fpga/mqnic: Add RAM inference directive to Intel designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-05 16:27:29 -07:00
Alex Forencich
f3bf63a775 merged changes in pcie 2022-08-05 16:25:42 -07:00
Alex Forencich
d6d59a5675 Don't force DMA RAM into MLABs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-05 16:25:18 -07:00
Alex Forencich
0c877a45fb fpga/build_images.py: update quartus message parsing 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-04 13:40:34 -07:00
Alex Forencich
d6186eff88 fpga/build_images.py: process both stdout and stderr 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-04 13:40:09 -07:00
Alex Forencich
cc99484d99 fpga/common: add missing parameter 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-03 23:04:23 -07:00
Alex Forencich
81648cf85b fpga/mqnic: Clean up PCIe DMA IF flow control connections 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-03 23:04:05 -07:00
Alex Forencich
053c08f027 merged changes in pcie 2022-08-03 14:14:48 -07:00
Alex Forencich
91450fcab7 PCIe flow control is handled in shim; remove flow control from PCIe DMA interface 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-03 13:47:02 -07:00
Alex Forencich
3f57c2143b fpga/mqnic: PCIe interface updates 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-03 12:28:49 -07:00
Alex Forencich
06f8deecd4 merged changes in pcie 2022-08-03 00:42:29 -07:00
Alex Forencich
607ce498cf fpga/mqnic: Update PCIe DMA settings on Intel designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-03 00:42:19 -07:00
Alex Forencich
4bcac62c2a fpga/mqnic: Disable PTP on 100G E-tile designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-03 00:41:53 -07:00
Alex Forencich
3f3be1e14d Implement flow control for P-Tile 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-02 22:57:27 -07:00
Alex Forencich
53ee26f3ec Use latest version of cocotbext-pcie 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-01 13:25:51 -07:00
Alex Forencich
7f0bd00170 Implement flow control for Stratix 10 shim 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-08-01 13:19:01 -07:00
Alex Forencich
9c434687a8 Add flow control credit counter to TLP FIFO MUX module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-31 17:35:07 -07:00
Alex Forencich
ad5a322ee1 Add PCIe flow control credit count module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-31 17:24:43 -07:00
Alex Forencich
1dfdd8b0e3 Timing optimization 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-31 17:24:03 -07:00
Alex Forencich
b1b82a3f2b Add pause inputs to TLP mux modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-29 17:16:05 -07:00
Alex Forencich
dc1976ee00 scripts: Add eyescan plotting script 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-29 12:03:23 -07:00
Alex Forencich
7f1c714bc4 utils: Add mqnic-xcvr utility 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-29 12:02:50 -07:00
Alex Forencich
4dd35181dc lib/mqnic: add register interface abstraction 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-28 17:52:19 -07:00
Alex Forencich
796ead9b1b utils: Fix PCI device path checks 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-27 14:26:37 -07:00
Alex Forencich
0afe9be906 fpga/mqnic/VCU108: Update VCU108 design to support 25G 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-26 23:26:11 -07:00
Alex Forencich
46a88e64c5 mqnic/common: Update UltraScale shim instance 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-26 14:05:11 -07:00
Alex Forencich
ddc1fe4477 merged changes in pcie 2022-07-26 14:01:37 -07:00
Alex Forencich
0d9b1d0fb0 Implement flow control in UltraScale shim 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-26 14:01:00 -07:00
Alex Forencich
6a29073aa6 fpga/mqnic/S10MX_DK: Update S10MX dev kit design to support 25G 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-25 21:25:21 -07:00
Alex Forencich
11a989d27a merged changes in eth 2022-07-25 16:39:32 -07:00
Alex Forencich
40acee1bc5 Rework MAC PTP timestamp adjustment logic 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-25 16:35:26 -07:00
Alex Forencich
07aeae5c2f Rework lane swapping logic 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-25 15:06:09 -07:00
Alex Forencich
fbaa714d2a Remove unnecessary CRC resets 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-25 15:03:03 -07:00
Alex Forencich
cb273970c3 Rework MAC frame padding logic 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-24 22:46:03 -07:00
Alex Forencich
2ce89aec09 Use generate blocks for Ethernet FCS computation 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-24 19:52:55 -07:00
Alex Forencich
5f39d6ece6 Improve internal encoding to simplify logic 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-24 17:32:43 -07:00
Alex Forencich
c7f3b4632b Simplify logic 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-24 16:08:34 -07:00
Alex Forencich
2601127679 Remove unnecessary zeroing 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-24 14:09:09 -07:00
Alex Forencich
ebd5f04e2d Remove unnecessary resets 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-24 10:14:54 -07:00
Alex Forencich
2a10dc1582 fpga/mqnic/S10MX_DK: Annotate serdes pins in QSF 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-23 19:43:21 -07:00
Alex Forencich
2c602b6368 Add 25g mqnic design for Stratix 10 DX dev kit 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-23 19:42:58 -07:00
Alex Forencich
549e60bdd1 Only use avst_empty at end of frame 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-22 23:00:09 -07:00