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Author SHA1 Message Date
Alex Forencich
62bec0fe56 merged changes in eth 2022-07-22 22:58:17 -07:00
Alex Forencich
c1e947dc3d Timing optimization of PTP modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-22 22:57:44 -07:00
Alex Forencich
a5fe40cd42 Fix JTAG index 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-22 22:34:26 -07:00
Alex Forencich
a53509de68 Add instance names 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-22 22:34:04 -07:00
Alex Forencich
90c65dfed7 Fix PBA offsets 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-22 22:33:38 -07:00
Alex Forencich
db881ed551 Remove magic numbers 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-22 18:39:21 -07:00
Alex Forencich
4a16c9070b Fix mixed assignments 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-22 01:24:22 -07:00
Alex Forencich
ec17500a66 Add 100G mqnic design for DE10-Agilex 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-21 18:49:35 -07:00
Alex Forencich
ae5a029720 Update PCIe model configuration 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-21 18:49:17 -07:00
Alex Forencich
03a49d7bc6 Add 25G mqnic design for DE10-Agilex 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-19 23:43:22 -07:00
Alex Forencich
ac6d523746 lib/mqnic: Add JTAG IDs for Intel Agilex series 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-19 17:13:50 -07:00
Alex Forencich
218f2e2bb3 25G designs use double width sync datapath by default 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 23:31:36 -07:00
Alex Forencich
4b6a96d5ee Add mqnic core logic for Intel P-Tile 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 23:15:54 -07:00
Alex Forencich
b50c389b4a merged changes in pcie 2022-07-18 23:08:51 -07:00
Alex Forencich
c76e152804 Rename cmac_ts_insert to mac_ts_insert 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 22:27:27 -07:00
Alex Forencich
84c6eb95a6 Update docs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 22:27:08 -07:00
Alex Forencich
debf36a01e modules/mqnic: Add driver support for 250-SoC 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 22:26:39 -07:00
Alex Forencich
e47175e5f2 Add 100G mqnic design for BittWare 250-SoC 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 22:26:22 -07:00
Alex Forencich
7235484825 Add 25G mqnic design for BittWare 250-SoC 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 22:26:12 -07:00
Alex Forencich
ef5b2449dc Add stretched PTP PPS output 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 22:25:58 -07:00
Alex Forencich
676f3edd2d Add TX PTP clock to port map module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 22:25:39 -07:00
Alex Forencich
b1240bdcae Remove extraneous wires 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 22:25:10 -07:00
Alex Forencich
2baae23f94 Minor cleanup 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 22:24:55 -07:00
Alex Forencich
e0d92172d3 Separate PTP TX clock input 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-18 22:24:41 -07:00
Alex Forencich
5fe904545c Testbench cleanup 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-13 16:35:51 -07:00
Alex Forencich
969169c315 Clean up module instantiation 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-13 16:19:30 -07:00
Alex Forencich
f29f72bab9 Change interval 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-13 01:18:55 -07:00
Alex Forencich
f19d993d8b Rework build_images settings 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-13 01:18:42 -07:00
Alex Forencich
fc90d7f44d Strip version number 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-13 00:40:43 -07:00
Alex Forencich
05f51ed05c Update readme 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-13 00:32:33 -07:00
Alex Forencich
be6bb907c9 Register MSI-X control signals 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-13 00:32:19 -07:00
Alex Forencich
dbcd211ce1 Add example design for DE10-Agilex 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-13 00:31:59 -07:00
Alex Forencich
c5382f5e7f Add example design for Stratix 10 DX dev kit 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-13 00:31:39 -07:00
Alex Forencich
cf3029364d Add P-Tile example design core module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-13 00:31:13 -07:00
Alex Forencich
2a727e04f7 Add PCIe interface shim for Intel Stratix 10 DX/Agilex P-Tile 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-12 23:53:34 -07:00
Alex Forencich
3f334dbbbb Use MSI-X in example designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-12 23:32:51 -07:00
Alex Forencich
e2588cd995 Clean up TCL scripts 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-12 16:23:54 -07:00
Alex Forencich
743f3817ce Fix alignment 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-11 23:36:53 -07:00
Alex Forencich
e15fe3cbc9 Fix port widths 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-11 23:32:19 -07:00
Alex Forencich
6b0df7f33f Rework RX request generation 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-09 14:43:39 -07:00
Alex Forencich
33b798540e Change hex format in makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-09 14:20:48 -07:00
Alex Forencich
729c3a0458 Update for PCIe shim changes, enable TLP straddling on US/US+ devices, and use 256 tags on US+ devices 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-08 22:07:18 -07:00
Alex Forencich
3c1865a81e merged changes in pcie 2022-07-06 23:19:43 -07:00
Alex Forencich
edd1d546d5 Fix 256-bit RC interface framing 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-06 23:14:19 -07:00
Alex Forencich
ce233c6c2b Use latest version of cocotbext-pcie 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-04 13:17:55 -07:00
Alex Forencich
a17c33e3c6 Update example designs to enable TLP straddling 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-04 01:31:15 -07:00
Alex Forencich
19b1af0388 Update Xilinx UltraScale shims to support TLP straddling 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-04 00:46:07 -07:00
Alex Forencich
103d7abdd9 Rework framing signal generation 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-03 22:38:16 -07:00
Alex Forencich
a44f9852c2 Update Stratix 10 H-tile/L-tile shim to support segments 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-02 23:48:46 -07:00
Alex Forencich
26c7128b7e Tie off unused port 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-02 23:42:03 -07:00