Alex Forencich
24dd0af398
Adjust MSI-X TLP port configuration for single segment, single DWORD operations
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Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-07-02 23:41:51 -07:00
Alex Forencich
5658af86e0
Add PCIe TLP FIFO mux module
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Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-07-02 23:41:27 -07:00
Alex Forencich
cc1278f9d9
Update PCIe TLP mux to handle multiple segments
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Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-07-02 23:40:35 -07:00
Alex Forencich
23705eb873
Update PCIe TLP demux to handle segments
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Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-07-02 23:39:38 -07:00
Alex Forencich
fc42368bd5
Add segmented PCIe TLP FIFO module
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Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-07-02 15:35:57 -07:00
Alex Forencich
a5e81d7575
Ensure wide RAMs are marked for MLAB inference
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Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-07-02 15:28:44 -07:00
Alex Forencich
b044ac10ff
Optimize offset_next computation
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Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-07-02 15:25:45 -07:00
Alex Forencich
93c2804b1b
Add pipeline register after barrel shift
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Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-07-02 15:24:28 -07:00
Alex Forencich
8797aa481f
Rework status FIFOs
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Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-07-02 15:24:05 -07:00
Alex Forencich
87e155949c
Add a simple block transfer measurement
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Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-06-19 22:52:16 -07:00
Alex Forencich
9b74e02408
Add jinja2 to tox.ini
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Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-06-13 01:36:12 -07:00
Alex Forencich
1ca13c3af2
Add TLP mux and demux tests
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Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-06-13 01:06:29 -07:00
Alex Forencich
2d48255ba3
Add mux and demux wrapper generators
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Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-06-13 01:06:01 -07:00
Alex Forencich
056500dbf4
Avoid zero-width replication
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Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-06-13 00:52:29 -07:00
Alex Forencich
72e8bad417
Normalize interfaces
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Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-06-13 00:51:37 -07:00
Alex Forencich
4818f2595c
Fix initial reg value
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Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-06-13 00:27:44 -07:00
Alex Forencich
d1e21cb78b
Add shim stress tests
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Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-06-12 23:30:27 -07:00
Alex Forencich
a096519fd8
Fix backpressure feedback bug
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Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-06-12 23:27:38 -07:00
Alex Forencich
630648d5b0
Fix default parameter values
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Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-06-11 22:58:26 -07:00
Alex Forencich
58d705b924
Add channel testbenches for S10 shim
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Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-06-11 01:50:38 -07:00
Alex Forencich
07970ae41d
Add channel testbenches for UltraScale shim
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Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-06-11 01:13:21 -07:00
Alex Forencich
33e21a6f9b
Remove extraneous parameter
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Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-06-11 01:09:06 -07:00
Alex Forencich
48daa02897
Update example designs
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Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-06-07 14:35:39 -07:00
Alex Forencich
27f749d5a5
Add strobe outputs to shims
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Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-06-07 14:23:24 -07:00
Alex Forencich
52e7af8a5d
Add combined TX/RX bus with all signals
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Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-06-05 19:09:15 -07:00
Alex Forencich
df32016724
Add sequence number ports to TLP mux and demux modules
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Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-06-05 17:34:12 -07:00
Alex Forencich
c95e8f70f2
Update PCIe TLP interface parametrization
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Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-06-05 14:31:10 -07:00
Alex Forencich
5595953d5a
merged changes in pcie
2022-06-05 14:30:42 -07:00
Alex Forencich
aadcd53c87
Update AXI DMA IF tests
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Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-06-05 14:29:16 -07:00
Alex Forencich
7d92722fe8
Clean up testbench parametrization
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Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-06-05 14:25:28 -07:00
Alex Forencich
70dc92c24e
Rework TLP interface parametrization
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Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-06-05 13:27:04 -07:00
Alex Forencich
ee59fc10e0
Update testbenches for new version of cocotbext-pcie
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Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-06-05 13:26:27 -07:00
Alex Forencich
a5d7833bd9
Update testbenches for new version of cocotbext-pcie
2022-06-05 00:24:42 -07:00
Alex Forencich
87bf5f2e41
Properly implement zero-length operations in generic interface model
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Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-06-04 14:52:54 -07:00
Alex Forencich
21b0f014a5
Switch to MSI-X
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Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-06-02 23:58:29 -07:00
Alex Forencich
6cda5f857c
merged changes in pcie
2022-06-02 23:36:46 -07:00
Alex Forencich
228d20b3f4
Update example designs
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Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-06-02 23:36:01 -07:00
Alex Forencich
5208b2844c
Add MSI-X support to shims
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Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-06-02 23:35:34 -07:00
Alex Forencich
2fa0bf3eb0
Add MSI-X module
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Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-06-02 23:34:15 -07:00
Alex Forencich
ba5188dd93
Update testbenches for new version of cocotbext-pcie
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Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-06-02 23:33:52 -07:00
Alex Forencich
cc8b9fa9ca
Add plotting script
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Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-05-31 21:06:32 -07:00
Alex Forencich
628324179e
Collect PCIe information and include MAC addresses in test report
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Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-05-31 21:05:11 -07:00
Alex Forencich
b50073417d
Add MTU settings to scripts
2022-05-31 21:04:22 -07:00
Alex Forencich
dd2853bf40
Update testbenches for latest version of cocotbext-pcie
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Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-05-30 13:10:39 -07:00
Alex Forencich
ae55dcc432
Add missing parameter
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Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-05-30 13:09:34 -07:00
Joachim Foerster
d6b2a38a92
modules/mqnic: Fix link status monitoring, initialize stored link status on start to "down"
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Assume that the hardware link status is "down" when a netdev is brought "up"
administratively ("ip link set dev ... up"). This way a change of link status is
always occuring, in case hardware link status is indeed still "up" at that point
in time.
Otherwise bringing a netdev administratively "down" and "up" again, while the
hardware was "up" before and stays "up" during the administrative "down" period,
results in no netif_carrier_on() being called, because struct
mqnic_priv::link_status does not change.
Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
2022-05-30 13:08:10 -07:00
Alex Forencich
4cdb57bfe1
Update module documentation
2022-05-23 21:23:13 -07:00
Joachim Foerster
0d2e794b74
modules/mqnic: Add link status monitoring
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This solution is based on the assumption that, if there are multiple
(mqnic-)ports per (mqnic-)interface, the single netdev, which is currently
associated with one (mqnic-)interface, is assumed to be up, when all ports' TX
and RX status bits are asserted. As soon as one of these bits is deasserted for
any of the involved ports the netdev is assumed to be down.
Module parameter "link_status_poll" specifies the polling interval in
milliseconds. Setting it to 0, disables any form of monitoring. By default we
check once per second, which is a totally arbitrary choice - no special
reasoning.
Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
2022-05-23 13:59:46 -07:00
Joachim Foerster
db1bb30745
modules/mqnic: Export link status via ethtool
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Makes ethtool show the usual "Link detected" line.
Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
2022-05-23 13:59:46 -07:00
Joachim Foerster
2697ec93e9
modules/mqnic: Minor, fix warning, when CONFIG_AUXILIARY_BUS is not available
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Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
2022-05-23 13:59:46 -07:00