Alex Forencich
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c2fea3a616
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Add port register blocks with support for PHY link status reporting
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-05-04 09:03:37 -07:00 |
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Alex Forencich
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cfdd6f5455
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Decouple transmit completion handling from PTP timestamping
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-05-01 17:41:47 -07:00 |
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Alex Forencich
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53f3547ef5
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Rework hierarchy to move port-specific logic out of mqnic_core and into mqnic_interface and new port-level modules
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-04-29 14:32:57 -07:00 |
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Alex Forencich
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2d5e82f42a
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apps: Fix application module symbol search path to include core mqnic module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-04-25 00:48:56 -07:00 |
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Alex Forencich
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2bd8350276
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Add RX queue mapping module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-04-23 00:12:22 -07:00 |
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Alex Forencich
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d45857fb98
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fpga/app/dma_bench: Add DMA benchmark application
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2022-04-21 14:19:43 -07:00 |
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