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Author SHA1 Message Date
Alex Forencich
c34a9c2197 Add 32 bit XGMII support 2016-07-19 19:59:47 -07:00
Alex Forencich
7d7cba0838 Add bus width checks 2016-07-19 16:21:15 -07:00
Alex Forencich
5afe1d7e1e Add example design for VCU108 board 2016-07-05 11:52:28 -04:00
Alex Forencich
1f52bf826d Update vivado.mk 2016-07-05 11:17:16 -04:00
Alex Forencich
cbf1df718a Add example design for Digilent Nexys Video board 2016-06-29 12:00:05 -07:00
Alex Forencich
a430e4463e Add RGMII endpoint and PHY interface module 2016-06-29 06:13:46 -07:00
Alex Forencich
b38c643384 Add more implementation parameters to gmii_phy_if 2016-06-28 19:35:52 -07:00
Alex Forencich
8c7a099a91 Update readme 2016-06-28 18:58:25 -07:00
Alex Forencich
635315c402 Remove generated eth_crc modules 2016-06-28 18:58:10 -07:00
Alex Forencich
47ca9a8725 Replace eth_crc modules for generic lfsr module 2016-06-28 17:31:58 -07:00
Alex Forencich
ccd8cd8c2e Add generic LFSR module 2016-06-28 17:25:09 -07:00
Alex Forencich
1b5d43a718 merged changes in axis 2016-06-27 12:27:00 -07:00
Alex Forencich
6fe4a033e5 Add dedicated pipeline registers for RAM addresses that are not reset 2016-06-27 12:25:18 -07:00
Alex Forencich
385c9cc90a Fix Vivado block RAM inference 2016-06-27 12:10:36 -07:00
Alex Forencich
4f66059d21 Adjust constant naming 2016-06-27 11:27:04 -07:00
Alex Forencich
f89620008d Remove reset dependence 2016-06-27 11:26:15 -07:00
Alex Forencich
cab7d367f2 Fix default width 2016-06-27 11:24:36 -07:00
Alex Forencich
b1dca3b57a Add missing declaration 2016-02-12 18:27:54 -08:00
Alex Forencich
f36256c541 Add 10G reference design for HXT100G 2016-01-25 19:11:42 -08:00
Alex Forencich
5eb0d9f578 Move invert to top-level module 2016-01-25 13:21:35 -08:00
Alex Forencich
eb8dd775a1 Add 10G reference design for DE5-Net 2016-01-25 00:53:06 -08:00
Alex Forencich
3f2d096249 Add XGMII interleaver and deinterleaver 2016-01-25 00:50:51 -08:00
Alex Forencich
c5b6202174 Update example design 2016-01-08 01:32:04 -08:00
Alex Forencich
152486bebd Update parametrization 2016-01-08 01:30:00 -08:00
Alex Forencich
9c01e114b4 Happy new year 2016-01-05 00:34:32 -08:00
Alex Forencich
1aee321620 merged changes in axis 2016-01-05 00:30:07 -08:00
Alex Forencich
be4034071b Happy new year 2016-01-05 00:24:20 -08:00
Alex Forencich
a98dfce099 Update output registers, remove extraneous resets, fix constant widths 2015-11-09 23:50:34 -08:00
Alex Forencich
4e8ef42031 merged changes in axis 2015-11-09 15:00:49 -08:00
Alex Forencich
7a9fdb5fc3 Add default case statements to avoid inferring latches 2015-11-09 14:54:14 -08:00
Alex Forencich
0d22a35bd8 Update output registers, remove extraneous resets, fix constant widths 2015-11-08 23:05:38 -08:00
Alex Forencich
0a79f24d3c Do not reset datapath registers in crosspoint switch 2015-11-08 17:27:13 -08:00
Alex Forencich
5fb4cb159b Reorganize register modules 2015-11-08 16:18:29 -08:00
Alex Forencich
0f0ebfb87d Reorganize FIFO modules 2015-11-07 01:15:11 -08:00
Alex Forencich
71235c0b92 64 bit Ethernet FCS checker optimizations 2015-11-03 15:32:23 -08:00
Alex Forencich
17bf03d7a2 10G MAC RX optimizations 2015-11-03 15:30:08 -08:00
Alex Forencich
26aacea6ef Remove unused code 2015-10-28 12:40:23 -07:00
Alex Forencich
73e0a1cff4 Fail outgoing frames on tvalid deassert 2015-10-20 16:05:23 -07:00
Alex Forencich
475f897a31 Unconditional increment length 2015-10-20 16:04:47 -07:00
Alex Forencich
2a59c7db1c Update generate scripts to use argparse 2015-10-19 19:26:59 -07:00
Alex Forencich
15fda58c7c merged changes in axis 2015-10-19 19:17:48 -07:00
Alex Forencich
7ea566e6d2 Update generate scripts to use argparse 2015-10-19 19:15:38 -07:00
Alex Forencich
61fe446797 merged changes in axis 2015-10-19 00:31:32 -07:00
Alex Forencich
dcad442e7c Improve timing performance of frame length adjust module 2015-10-19 00:30:50 -07:00
Alex Forencich
9d90f09de5 Rework CRC check 2015-10-09 22:56:52 -07:00
Alex Forencich
08afe3a5d2 Synchronize MAC status signals 2015-10-09 22:51:55 -07:00
Alex Forencich
cc5fead04d Convert to synchronous resets 2015-10-09 22:36:58 -07:00
Alex Forencich
55071645fd Update async FIFO instances 2015-10-09 22:35:25 -07:00
Alex Forencich
98b15b6226 merged changes in axis 2015-10-09 15:21:26 -07:00
Alex Forencich
364b537312 Synchronize status signals for both clock domains in async frame FIFO 2015-10-09 15:14:54 -07:00