Alex Forencich
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c44ffe2f92
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Add timespec handling code
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2019-07-22 18:00:55 -07:00 |
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Alex Forencich
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32cadd4480
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Update mqnic-fw to use new code
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2019-07-21 21:56:23 -07:00 |
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Alex Forencich
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1b45043965
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Update makefile
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2019-07-21 21:54:22 -07:00 |
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Alex Forencich
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1b147ff7c8
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Add shared utility code
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2019-07-21 21:53:37 -07:00 |
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Alex Forencich
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762037e8a8
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Updates to be able to share header with userspace code
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2019-07-21 21:51:14 -07:00 |
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Alex Forencich
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a6c4b8b1b7
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Change board IDs
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2019-07-21 15:27:01 -07:00 |
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Alex Forencich
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851eb2f25e
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Update readme
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2019-07-20 00:56:21 -07:00 |
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Alex Forencich
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ea7ccd182e
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Move MAC out of port module
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2019-07-19 23:29:03 -07:00 |
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Alex Forencich
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1917ed3912
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merged changes in eth
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2019-07-19 18:17:57 -07:00 |
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Alex Forencich
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ab77ac3858
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Fix width
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2019-07-19 18:16:07 -07:00 |
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Alex Forencich
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451db171d1
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Don't leave output floating
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2019-07-19 18:13:30 -07:00 |
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Alex Forencich
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9de2101cdc
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Update ExaNIC X10 testbenches
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2019-07-19 18:01:24 -07:00 |
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Alex Forencich
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eb92578699
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Update FIFO instances
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2019-07-19 16:17:36 -07:00 |
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Alex Forencich
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00ebe73bdc
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merged changes in eth
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2019-07-19 15:52:41 -07:00 |
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Alex Forencich
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36b3dccb6a
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Add mqnic-fw utility
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2019-07-19 15:48:33 -07:00 |
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Alex Forencich
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578abab3de
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Add mqnic-config utility
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2019-07-19 15:46:56 -07:00 |
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Alex Forencich
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5b15f03f69
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Add ADM-PCIE-9V3 mqnic_tdma design
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2019-07-19 15:43:40 -07:00 |
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Alex Forencich
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a9179dc550
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Add ExaNIC X10 mqnic_tdma design
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2019-07-19 15:42:18 -07:00 |
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Alex Forencich
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4b37a4484d
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Add TDMA round-robin scheduler
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2019-07-19 15:40:53 -07:00 |
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Alex Forencich
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750112ff06
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Add ADM-PCIE-9V3 mqnic design
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2019-07-19 15:39:40 -07:00 |
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Alex Forencich
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4c3f2412df
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Add TDMA BERT modules and testbenches
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2019-07-19 15:28:57 -07:00 |
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Alex Forencich
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c5e886769a
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Fix typo
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2019-07-19 10:29:55 -07:00 |
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Alex Forencich
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16d1662d98
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Add PTP timestamping infrastructure to 10G MACs
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2019-07-18 23:13:46 -07:00 |
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Alex Forencich
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4e49dbcf3d
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Pass parameters to model
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2019-07-18 22:51:54 -07:00 |
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Alex Forencich
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8cb0a5e06e
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Add parameters for PTP clock model
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2019-07-18 22:49:29 -07:00 |
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Alex Forencich
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16755720d3
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Add PTP tag inserter module
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2019-07-18 22:39:50 -07:00 |
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Alex Forencich
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b26f923c2f
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Reset synchronizers
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2019-07-18 18:35:30 -07:00 |
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Alex Forencich
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adb9c4d147
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Fix initial values
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2019-07-18 18:35:11 -07:00 |
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Alex Forencich
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16e5ec2106
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Update example designs
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2019-07-18 17:13:47 -07:00 |
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Alex Forencich
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3bd7be44fa
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Update FIFO instances and update MACs to use combined FIFO adapter module
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2019-07-18 16:25:49 -07:00 |
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Alex Forencich
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3a79b8fb17
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merged changes in axis
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2019-07-18 11:50:56 -07:00 |
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Alex Forencich
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8b2f37d5cc
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Update readme
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2019-07-18 11:28:19 -07:00 |
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Alex Forencich
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69de6fd2a4
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Convert FIFOs to use DEPTH parameter instead of ADDR_WIDTH
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2019-07-18 11:27:25 -07:00 |
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Alex Forencich
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e0a1a73ce0
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Mask tdata with tkeep
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2019-07-18 11:01:00 -07:00 |
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Alex Forencich
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4da1a83052
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Constant FIFO depth
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2019-07-17 23:36:10 -07:00 |
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Alex Forencich
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905651d5f8
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Add PTP perout utility
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2019-07-17 18:48:50 -07:00 |
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Alex Forencich
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6c5b6c99a1
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Initial commit of mqnic kernel module
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2019-07-17 18:13:51 -07:00 |
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Alex Forencich
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1df012a8d4
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Add ExaNIC X10 design
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2019-07-17 16:57:04 -07:00 |
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Alex Forencich
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fcd8b1b8e9
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Add driver simulation model
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2019-07-17 16:46:12 -07:00 |
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Alex Forencich
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ce011453d6
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Add interface module
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2019-07-17 16:43:12 -07:00 |
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Alex Forencich
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351404813a
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Add port module
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2019-07-17 16:42:39 -07:00 |
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Alex Forencich
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65f0ff28b5
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Add Ethernet interface module
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2019-07-17 16:41:21 -07:00 |
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Alex Forencich
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12f215fe26
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Add round robin transmit scheduler
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2019-07-17 16:40:35 -07:00 |
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Alex Forencich
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bda4e87371
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Add event management modules
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2019-07-17 16:39:59 -07:00 |
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Alex Forencich
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f94e83e520
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Add transmit and receive engines
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2019-07-17 16:38:57 -07:00 |
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Alex Forencich
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6100e3ad78
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Add RX checksum module and testbench
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2019-07-16 00:42:49 -07:00 |
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Alex Forencich
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755c7959be
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merged changes in eth
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2019-07-16 00:40:02 -07:00 |
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Alex Forencich
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021c91fcc7
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Unconditionally wait at least one delta cycle
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2019-07-16 00:37:20 -07:00 |
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Alex Forencich
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583849e0db
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merged changes in axis
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2019-07-16 00:30:49 -07:00 |
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Alex Forencich
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1d5a4db0d5
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Unconditionally wait at least one delta cycle
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2019-07-16 00:30:19 -07:00 |
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