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Author SHA1 Message Date
Alex Forencich
a653f2d839 Add TDMA scheduler module and testbench 2019-07-16 00:19:22 -07:00
Alex Forencich
fc9a6c1c50 Add completion queue manager module and testbench 2019-07-16 00:16:07 -07:00
Alex Forencich
46f653f097 Add queue manager module and testbench 2019-07-16 00:15:50 -07:00
Alex Forencich
3d4ba0fa3f Add testbench symlinks 2019-07-16 00:15:25 -07:00
Alex Forencich
ce709ed4c0 merged changes in pcie 2019-07-15 20:39:17 -07:00
Alex Forencich
6e5a3934b2 Add get_free_tag methods 2019-07-15 20:38:09 -07:00
Alex Forencich
4bf1205514 Fix completion handling in function 2019-07-15 20:25:23 -07:00
Alex Forencich
c83b04f9db merged changes in eth 2019-07-15 18:09:52 -07:00
Alex Forencich
1279dcbf47 Back out previous change 2019-07-15 18:09:14 -07:00
Alex Forencich
16262b2ead merged changes in pcie 2019-07-15 17:25:16 -07:00
Alex Forencich
a0bd74a198 Add Xilinx VCU118 example design 2019-07-15 17:24:50 -07:00
Alex Forencich
b0b51fdb34 Add Alpha Data ADM-PCIE-9V3 example design 2019-07-15 17:23:31 -07:00
Alex Forencich
f1348db2f7 Add Ultrascale Plus PCIe hard IP core model and testbench 2019-07-15 17:18:39 -07:00
Alex Forencich
debcdb58ad merged changes in eth 2019-07-15 16:43:21 -07:00
Alex Forencich
cc1ff34f53 Add 64 bit timestamp support to ptp_clock_cdc 2019-07-15 16:36:02 -07:00
Alex Forencich
a9f3cf001d merged changes in eth 2019-07-15 16:17:07 -07:00
Alex Forencich
31cb54e67e Make old icarus verilog happy 2019-07-15 16:15:50 -07:00
Alex Forencich
ef3a39e933 Update readme 2019-07-15 15:31:25 -07:00
Alex Forencich
c719b57474 Update readme 2019-07-15 15:27:46 -07:00
Alex Forencich
9d553f2ad4 Also need to use tready 2019-07-15 15:24:12 -07:00
Alex Forencich
d88ada105d Add PTP TS extract module 2019-07-15 15:17:58 -07:00
Alex Forencich
77bae7a77e Add PTP clock CDC module and testbench 2019-07-15 15:16:17 -07:00
Alex Forencich
dcea219303 added pcie as a subproject 
git-subtree-dir: fpga/lib/pcie
git-subtree-mainline: 5ad725bd0ff04fe7fe7ab9983c0c3e64355e0dd2
git-subtree-split: 1d79a4375b42a8dad274b3e0a757f833400d556e
 2019-07-15 14:55:57 -07:00
Alex Forencich
5ad725bd0f added axi as a subproject 
git-subtree-dir: fpga/lib/axi
git-subtree-mainline: d644d8c5e30c9b704704d8974ee73f1573ac2af2
git-subtree-split: 23a14dc5dfa1d18c0c1e73ff00bf462d1b7ea5da
 2019-07-15 14:55:51 -07:00
Alex Forencich
d644d8c5e3 Add axis symlink 2019-07-15 14:55:44 -07:00
Alex Forencich
de181120b8 added eth as a subproject 
git-subtree-dir: fpga/lib/eth
git-subtree-mainline: 4cdce8caa74728a4973261dae0e00fcd479af9ac
git-subtree-split: e5171d874916b3e23a02d5621e91dd9ff02b7fcb
 2019-07-15 14:55:25 -07:00
Alex Forencich
4cdce8caa7 Add subtree scripts 2019-07-15 14:55:10 -07:00
Alex Forencich
dce357bfed Initial commit 2019-07-15 14:53:31 -07:00
Alex Forencich
1d79a4375b Add PCIe related scripts 2019-07-15 12:33:35 -07:00
Alex Forencich
b5e520e9da Add gitignore 2019-07-15 12:29:19 -07:00
Alex Forencich
d3b24e734f Don't use traceSignals 2019-07-14 21:45:10 -07:00
Alex Forencich
ece7186671 Fix typo 2019-07-14 21:41:21 -07:00
Alex Forencich
d99afcb2f1 Change tag count 2019-07-13 11:21:19 -07:00
Alex Forencich
9c176b0916 Add ExaNIC X10 example design 2019-07-13 11:06:29 -07:00
Alex Forencich
8ecf4a22ef Add pcie_us_cfg module 2019-07-13 10:24:25 -07:00
Alex Forencich
dcd8d7cd77 Update readme 2019-07-12 12:15:58 -07:00
Alex Forencich
23a14dc5df Update readme 2019-07-09 00:18:58 -07:00
Alex Forencich
21dbe318b4 Add AXI lite clock domain crossing module, testbench, and timing constraints 2019-07-09 00:18:27 -07:00
Alex Forencich
36523dd7cc Fix typo 2019-07-08 17:57:47 -07:00
Alex Forencich
f924f75b70 Use computed word size 2019-07-08 17:57:30 -07:00
Alex Forencich
7591cb4d1c Update readme 2019-07-08 17:53:39 -07:00
Alex Forencich
ed344f352f Add AXI to AXI lite adapter modules and testbenches 2019-07-08 17:51:12 -07:00
Alex Forencich
f5830b6407 Backpressure updates 2019-07-08 17:34:09 -07:00
Alex Forencich
abcb20612e Remove redundant code 2019-07-08 00:28:27 -07:00
Alex Forencich
1bd22f5208 Ensure rready clear when returning to idle 2019-07-05 23:29:39 -07:00
Alex Forencich
3f21db4584 bresp handling update 2019-07-04 14:23:37 -07:00
Alex Forencich
e5171d8749 Enable flash programming in VCU118 example designs 2019-07-01 17:51:31 -07:00
Alex Forencich
0515d354e3 Critical path optimization 2019-06-28 17:28:12 -07:00
Alex Forencich
4afbd71f1f Fanout optimization 2019-06-28 17:24:37 -07:00
Alex Forencich
fdfb517761 Add PTP perout module and testbench 2019-06-27 01:30:18 -07:00