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Author SHA1 Message Date
Alex Forencich
e938844783 Account for merged registers 2019-03-27 23:54:48 -07:00
Alex Forencich
f53b7ab75e Fix MSI wrapper 2019-03-27 17:42:37 -07:00
Alex Forencich
d651cb72de merged changes in axis 2019-03-26 18:49:15 -07:00
Alex Forencich
48984013de Add AXI stream async FIFO timing constraints 2019-03-26 18:46:25 -07:00
Alex Forencich
932aa35451 Fix AXI stream async frame FIFO write pointer synchronization 2019-03-26 18:45:54 -07:00
Alex Forencich
3920b2801e Add short packet tests 2019-03-26 16:39:31 -07:00
Alex Forencich
88badf13f0 Reset all status synchronization stages 2019-03-26 16:19:49 -07:00
Alex Forencich
585ccefa15 Add TX underflow error signal 2019-03-26 12:42:08 -07:00
Alex Forencich
b691a30760 Accept OS_START block type 2019-03-26 12:06:58 -07:00
Alex Forencich
9891d75c2f Fix STATE_WAIT_END 2019-03-25 23:24:01 -07:00
Alex Forencich
0efb135b7a Fix STATE_WAIT_END 2019-03-25 15:06:45 -07:00
Alex Forencich
5d42112477 Enable PCIe extended tag based on tag count 2019-03-21 00:01:48 -07:00
Alex Forencich
a60e1f726f Fix use before define 2019-03-18 14:02:10 -07:00
Alex Forencich
fb4abb6b39 Fix widths 2019-03-14 14:44:00 -07:00
Alex Forencich
f128190130 Ensure transfer is terminated at the end of the input frame 2019-03-13 14:48:05 -07:00
Alex Forencich
101be9fa2c Fix use before define 2019-03-12 13:15:11 -07:00
Alex Forencich
620526d581 Also match transfers by region 2019-03-12 12:58:56 -07:00
Alex Forencich
013e88253e Testbench updates 2019-03-07 23:44:43 -08:00
Alex Forencich
4d3036b9d0 merged changes in axis 2019-03-07 23:43:13 -08:00
Alex Forencich
414f091c2c Properly handle width of 1 2019-03-07 22:59:49 -08:00
Alex Forencich
b1f3a74b86 Remove unused code 2019-03-07 22:59:15 -08:00
Alex Forencich
d2df971fc9 Add AXI stream frame length measurement module and testbenches 2019-03-07 22:57:46 -08:00
Alex Forencich
e0f740457b Testbench updates 2019-03-07 22:51:40 -08:00
Alex Forencich
e71a62e6a1 Fix backpressure issue 2019-03-07 17:45:25 -08:00
Alex Forencich
4d628c9171 Fix thread matching 2019-03-06 13:40:29 -08:00
Alex Forencich
724f18113c Fix bug 2019-03-05 22:20:44 -08:00
Alex Forencich
b592c7d7af Add missing parameter 2019-03-03 22:32:35 -08:00
Alex Forencich
56ebc966e1 Update parameters 2019-03-03 13:37:34 -08:00
Alex Forencich
33dceb493b More asserts 2019-03-01 01:09:27 -08:00
Alex Forencich
67d31ecef0 Set more parameters during enumeration 2019-03-01 01:07:57 -08:00
Alex Forencich
f92c1ea980 Reorder capability registrations 2019-02-28 23:46:39 -08:00
Alex Forencich
1480be2173 Rewrite capability management 2019-02-28 23:45:23 -08:00
Alex Forencich
b60886a0ec Add AXI stream broadcast module and testbench 2019-02-27 19:46:30 -08:00
Alex Forencich
e9cd97f0b4 Pass through more signals in AXI RAM interfaces 2019-02-26 01:25:03 -08:00
Alex Forencich
8478c5d076 Incorrect signals 2019-02-25 20:37:55 -08:00
Alex Forencich
a501df6965 Update readme 2019-02-25 18:56:39 -08:00
Alex Forencich
7b713199ad Add AXI nonblocking crossbar interconnect module and testbench 2019-02-25 18:37:46 -08:00
Alex Forencich
365e063bc7 Add AXI DMA and CDMA descriptor mux modules 2019-02-25 15:44:10 -08:00
Alex Forencich
04dd6a34d7 Fix combinatorial loop 2019-02-20 18:48:27 -08:00
Alex Forencich
6baede4717 Broadcast message support 2019-02-15 18:04:46 -08:00
Alex Forencich
1630200cd8 Implement proper downstream TLP routing 2019-02-15 17:55:24 -08:00
Alex Forencich
178133498b Fix indentation 2019-02-15 17:23:33 -08:00
Alex Forencich
13d35569fa Match IO bars for routing IO operations 2019-02-15 17:23:14 -08:00
Alex Forencich
35a4d62fb8 Split SwitchBridge into separate upstream and downstream ports 2019-02-15 16:56:21 -08:00
Alex Forencich
247bca01f3 Add default_switch_port parameter 2019-02-15 15:26:09 -08:00
Alex Forencich
8cb607be04 Fix calls to read and write root complex regions 2019-02-15 14:40:24 -08:00
Alex Forencich
7654d874ae Fix out of range access due to off by one error 2019-02-11 19:30:57 -08:00
Alex Forencich
cd6b87e984 Enable bitstream compression in example designs 2019-02-06 21:25:30 -08:00
Alex Forencich
52058cb5de Swap out PHY in VCU118 example design 2019-02-05 18:28:42 -08:00
Alex Forencich
57dd292ae9 Add AXI RAM interface modules, AXI dual port RAM module, and testbench 2019-02-01 18:22:03 -08:00