Alex Forencich
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c47f3ea03d
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Update FIFO instance, rename ports
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2018-10-25 10:17:58 -07:00 |
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Alex Forencich
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d1ed1528b5
|
Update FIFO instance, rename ports
|
2018-10-25 10:15:16 -07:00 |
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Alex Forencich
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11d9dbe24a
|
Merge axis_async_fifo and axis_async_frame_fifo, rename ports
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2018-10-25 09:53:38 -07:00 |
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Alex Forencich
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36d0a8786f
|
Merge axis_fifo and axis_frame_fifo, rename ports
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2018-10-24 23:16:06 -07:00 |
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Alex Forencich
|
2bb9f11c9e
|
Use logical operators
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2018-10-24 22:24:27 -07:00 |
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Alex Forencich
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9d813226d0
|
Convert generated demux to verilog parametrized demux
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2018-10-24 22:16:05 -07:00 |
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Alex Forencich
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145ea2c40c
|
Connect arbiter parameters to top level
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2018-10-24 21:09:00 -07:00 |
|
Alex Forencich
|
2bf15706cd
|
Convert generated mux to verilog parametrized mux
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2018-10-24 18:23:14 -07:00 |
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Alex Forencich
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029d1fa06f
|
Fix loop count variable scoping issue
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2018-10-24 17:58:39 -07:00 |
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Alex Forencich
|
fc6c07e5f9
|
Convert generated frame joiner to verilog parametrized frame joiner
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2018-10-24 17:07:22 -07:00 |
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Alex Forencich
|
fd7f65d5ad
|
Convert generated switch to verilog parametrized switch
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2018-10-24 16:12:56 -07:00 |
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Alex Forencich
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631147069f
|
Rename ports and add reg_type parameter to axis_register
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2018-10-24 14:35:08 -07:00 |
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Alex Forencich
|
940c1210c1
|
Convert arbitrated mux to verilog parametrized arbitrated mux
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2018-10-24 13:49:17 -07:00 |
|
Alex Forencich
|
fe77db822d
|
Convert generated crosspoint to verilog parametrized crosspoint
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2018-10-24 13:44:39 -07:00 |
|
Alex Forencich
|
8e5ec36ced
|
Optimize axis_arb_mux and improve latency
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2018-08-09 18:40:50 -07:00 |
|
Alex Forencich
|
7a879aec1c
|
Remove extra registers
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2018-08-09 18:38:41 -07:00 |
|
Alex Forencich
|
202fbcbb6f
|
Fix typo
|
2018-08-09 11:23:27 -07:00 |
|
Alex Forencich
|
7c6da337b0
|
Happy new year
|
2018-02-27 01:39:25 -08:00 |
|
Alex Forencich
|
5df7efe516
|
Happy new year
|
2018-02-26 12:25:20 -08:00 |
|
Alex Forencich
|
4ec4c901e8
|
Whitespace fixes
|
2017-11-21 00:18:09 -08:00 |
|
Alex Forencich
|
b00eaf4d3c
|
Add tkeep signal and update testbench for stat counter
|
2017-11-21 00:17:42 -08:00 |
|
Alex Forencich
|
ad0e3e1eb5
|
Whitespace fixes and testbench update for frame joiner
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2017-11-21 00:16:15 -08:00 |
|
Alex Forencich
|
a1a6d523e3
|
Update FIFO instances and testbenches for COBS encoder and decoder
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2017-11-21 00:14:26 -08:00 |
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Alex Forencich
|
0edafd58ac
|
Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream tap
|
2017-11-20 23:45:34 -08:00 |
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Alex Forencich
|
4ef4ef2622
|
Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream SRL register
|
2017-11-20 21:34:25 -08:00 |
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Alex Forencich
|
b0d7820f5b
|
Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream SRL FIFO
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2017-11-20 21:32:46 -08:00 |
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Alex Forencich
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d16f19f67e
|
Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream rate limiter
|
2017-11-20 21:31:41 -08:00 |
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Alex Forencich
|
772e433ee9
|
Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream frame length adjuster
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2017-11-20 21:30:26 -08:00 |
|
Alex Forencich
|
de590517a9
|
Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream switch
|
2017-11-20 20:17:20 -08:00 |
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Alex Forencich
|
91a7169f46
|
Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream crosspoint
|
2017-11-20 20:16:21 -08:00 |
|
Alex Forencich
|
496c63bd1c
|
Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream arbitrated mux
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2017-11-20 20:15:08 -08:00 |
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Alex Forencich
|
57e700f802
|
Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream demux
|
2017-11-20 20:14:20 -08:00 |
|
Alex Forencich
|
9e4aa38750
|
Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream mux
|
2017-11-20 20:13:53 -08:00 |
|
Alex Forencich
|
d50c767482
|
Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream adapter
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2017-11-20 20:12:43 -08:00 |
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Alex Forencich
|
fdb881719c
|
Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream async frame FIFO
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2017-11-20 20:12:02 -08:00 |
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Alex Forencich
|
1c7362c717
|
Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream frame FIFO
|
2017-11-20 20:11:44 -08:00 |
|
Alex Forencich
|
7d237f55c1
|
Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream async FIFO
|
2017-11-20 20:11:08 -08:00 |
|
Alex Forencich
|
190d75df9d
|
Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream FIFO
|
2017-11-20 20:10:41 -08:00 |
|
Alex Forencich
|
a5524287ca
|
Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream register
|
2017-11-20 20:09:48 -08:00 |
|
Alex Forencich
|
aebe0549dd
|
Happy new year
|
2017-05-18 13:35:11 -07:00 |
|
Alex Forencich
|
0691c9d61b
|
Fix output pipeline issue
|
2016-09-02 10:43:21 -07:00 |
|
Alex Forencich
|
4245e2bf00
|
Rework mux logic
|
2016-08-24 16:53:13 -07:00 |
|
Alex Forencich
|
3207a2b7d2
|
Remove redundant code
|
2016-08-23 09:25:19 -07:00 |
|
Alex Forencich
|
24f7aee8b2
|
Add COBS encoder and decoder modules and testbench
|
2016-08-21 20:03:54 -07:00 |
|
Alex Forencich
|
a961a9756a
|
Add FIFO output pipeline registers to aid block RAM output timing closure
|
2016-08-04 18:03:00 -07:00 |
|
Alex Forencich
|
b44e401b95
|
Update async FIFO resets
|
2016-07-27 13:42:44 -07:00 |
|
Alex Forencich
|
06bfa1944c
|
Add AXI stream switch module, generator script, and testbench
|
2016-07-25 13:12:10 -07:00 |
|
Alex Forencich
|
d023213fda
|
Support generating asymmetric crosspoints
|
2016-07-24 13:06:59 -07:00 |
|
Alex Forencich
|
52fc34d82e
|
Assume first tkeep bit is always set
|
2016-07-20 12:36:59 -07:00 |
|
Alex Forencich
|
6fe4a033e5
|
Add dedicated pipeline registers for RAM addresses that are not reset
|
2016-06-27 12:25:18 -07:00 |
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