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Author SHA1 Message Date
Alex Forencich
d3690a12ab Update readme 2021-08-04 01:04:31 -07:00
Alex Forencich
12f90eac5b Update test durations 2021-08-04 01:04:20 -07:00
Alex Forencich
836d14bad6 Add PCIe interface shim for Xilinx UltraScale 2021-08-04 01:03:31 -07:00
Alex Forencich
b95f030408 Add PCIe DMA interface modules and testbenches 2021-08-04 01:02:48 -07:00
Alex Forencich
1a5e96d0fd Add PCIe AXI lite master module and testbench 2021-08-04 01:01:22 -07:00
Alex Forencich
623cc1ae8d Add generic PCIe interface model 2021-08-03 22:33:23 -07:00
Alex Forencich
bf3143a79f Fix test name 2021-08-03 01:54:00 -07:00
Alex Forencich
fceea6f8d8 Add output FIFOs to DMA engines 2021-08-03 01:53:18 -07:00
Alex Forencich
e0e34a9f0d Update designs for PCIe module changes 2021-08-02 23:04:52 -07:00
Alex Forencich
6e178377c3 merged changes in pcie 2021-08-02 22:46:16 -07:00
Alex Forencich
e4508b242f Update example designs 2021-08-02 18:36:25 -07:00
Alex Forencich
36ec7aaa16 Add error reporting to DMA modules 2021-08-02 17:24:00 -07:00
Alex Forencich
ee9c719bf4 Add error reporting to DMA modules 2021-08-01 10:59:38 -07:00
Alex Forencich
db826e489b Set algorithm for pytest-split 2021-08-01 01:19:07 -07:00
Alex Forencich
52d8867f73 Use BUFG instead of BUFIO2 for DDR input on Spartan 6 2021-07-31 12:45:38 -07:00
Alex Forencich
3edbe52bfa Use BUFG instead of BUFIO2 for DDR input on Spartan 6 2021-07-31 12:43:33 -07:00
Alex Forencich
b0ed724d70 merged changes in pcie 2021-07-25 02:24:33 -07:00
Alex Forencich
dad637bd00 Properly handle zero-length DMA operations 2021-07-25 01:36:40 -07:00
Alex Forencich
59c026b1b8 Fix parameters 2021-07-24 02:02:30 -07:00
Alex Forencich
3e03b20bc7 Properly handle zero-length PCIe read and write operations 2021-07-24 01:13:25 -07:00
Alex Forencich
29313d5e02 Add HTG-9200 10G example design 2021-07-08 11:58:04 -07:00
Alex Forencich
4ed99c6f87 Remove CMS IP version number 2021-07-03 00:09:10 -07:00
Alex Forencich
c926fd2ca1 Remove extraneous imports 2021-06-28 22:35:22 -07:00
minseongg
9af504a6c0 Update cmac_pad testbench 2021-06-28 22:33:57 -07:00
minseongg
8db2faddc6 Update cmac_pad testbench 2021-06-28 22:33:57 -07:00
minseongg
dc5c8232f9 Add cmac_pad testbench 2021-06-28 22:33:57 -07:00
Alex Forencich
cf832f581c Set algorithm for pytest-split 2021-06-28 01:34:34 -07:00
Alex Forencich
b1c6bdbd88 merged changes in pcie 2021-06-27 14:05:12 -07:00
Alex Forencich
cd9f6a9329 Use defines instead of magic numbers 2021-06-27 14:04:43 -07:00
Alex Forencich
5d153635f4 Set algorithm for pytest-split 2021-06-27 14:03:59 -07:00
Alex Forencich
c7a59c5f15 Split read requests on RCB 2021-06-27 01:31:40 -07:00
Alex Forencich
97182ccf4e Update vivado.mk 2021-06-23 20:07:29 -07:00
Alex Forencich
36a361d7c3 Update test durations 2021-06-18 18:42:44 -07:00
Alex Forencich
6b0076debc Work around pytest-split bug 2021-06-18 18:41:26 -07:00
Alex Forencich
ccc44d7dbb Use 64 bit BARs in example designs 2021-06-16 23:23:53 -07:00
Alex Forencich
a79027fdd1 Remove DEV_BAR_CNT define 2021-06-16 21:36:34 -07:00
Alex Forencich
763cc1669f Update test durations 2021-06-03 13:52:41 -07:00
Alex Forencich
2a7d190eb4 Update test durations 2021-06-03 13:48:33 -07:00
Alex Forencich
0a7f1ccbbe Remove string parameters 2021-06-02 18:18:23 -07:00
Alex Forencich
4d89e70b92 merged changes in axi 2021-06-02 17:57:51 -07:00
Alex Forencich
bea7ff909f merged changes in pcie 2021-06-02 17:57:45 -07:00
Alex Forencich
7558949e12 merged changes in eth 2021-06-02 17:57:39 -07:00
Alex Forencich
5415c41c41 Remove string parameters 2021-06-02 17:50:26 -07:00
Alex Forencich
846183bc8b merged changes in axis 2021-06-02 17:06:26 -07:00
Alex Forencich
31378c4e85 Remove string parameters 2021-06-02 17:05:29 -07:00
Alex Forencich
5063aeadcd Remove string parameters 2021-06-02 17:04:53 -07:00
Alex Forencich
4fa3870dea Remove string parameters 2021-06-02 15:08:43 -07:00
Alex Forencich
e4e05ed1e3 Update readme 2021-06-01 16:29:52 -07:00
Alex Forencich
51caad0810 Extract port counts 2021-06-01 13:22:48 -07:00
Alex Forencich
a852697707 Fix instance names in wrappers 2021-06-01 13:18:11 -07:00