11 Commits

Author	SHA1	Message	Date
Alex Forencich	c5d5fe8a64	fpga/mqnic: Remove unused wires ... Signed-off-by: Alex Forencich <alex@alexforencich.com>	2022-04-09 23:02:44 -07:00
Alex Forencich	f082196b4a	Expose EVENT_QUEUE_INDEX_WIDTH parameter at top-level	2022-03-29 23:15:06 -07:00
Alex Forencich	cbd9d0dfc6	Expose port and scheduler block counts in IF control block; update driver model, driver, and userspace tools to handle scheduler blocks separately from ports	2022-03-28 17:23:27 -07:00
Alex Forencich	09128df360	Add SCHED_PER_IF parameter to split scheduler count from port count	2022-03-28 15:20:33 -07:00
Alex Forencich	dfae34ed25	Pass through PTP pipelining settings	2022-03-28 00:50:29 -07:00
Alex Forencich	e95c132045	Route PCIe user reset through BUFG	2022-03-25 01:26:29 -07:00
Alex Forencich	6f197c7cb4	Add PHY instances to Ethernet pblocks	2022-03-24 21:30:55 -07:00
Alex Forencich	0e15a7a16b	Avoid critical warning from placement constraints when configured with a single interface	2022-03-17 15:39:13 -07:00
Alex Forencich	1291d7b1b7	Add pipeline registers to TDMA BER modules	2022-03-15 17:40:27 -07:00
Alex Forencich	25421b8994	Update placement constraints	2022-03-15 15:28:43 -07:00
Alex Forencich	2024ac60ec	Unified 10G/25G design for AU280	2022-03-14 21:37:40 -07:00