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Author SHA1 Message Date
Alex Forencich
bdc974a60c Reorganize HTG-9200 PLL config 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-21 16:34:11 -07:00
Alex Forencich
efb3747967 Add IO delay false paths to HTG-9200 constraints file 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-20 21:15:20 -07:00
Alex Forencich
4a65e3594c Connect all PLL control lines on HTG-9200 board 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-20 01:17:49 -07:00
Alex Forencich
789512c6da fpga/mqnic/VCU118: Use QSFP Si570 for both QSFP modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-19 17:49:46 -07:00
Alex Forencich
375b12865f Use QSFP Si570 for both QSFP modules on VCU118 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-19 17:00:33 -07:00
Alex Forencich
7d2f77a30b fpga/common: Connect xcvr_ctrl_rst to QPLLs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-17 18:44:42 -07:00
Alex Forencich
a99815800b fpga/common: Fix GT wrapper timing constraints when DRP interface is tied off 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-17 18:43:07 -07:00
Alex Forencich
1be196279f Fix FIFO instances in S10DX example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-17 11:05:24 -07:00
Alex Forencich
2858aaaef7 Add TX PTP timestamp enable bit in tuser 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-17 10:58:40 -07:00
Alex Forencich
50b6f53387 Update testbench clock frequencies 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-15 01:53:31 -07:00
Alex Forencich
d3fb11b2c3 Use unified 10G/25G design for HTG9200 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 21:35:42 -07:00
Alex Forencich
412df8fea0 Use unified 10G/25G design for fb2CG@KU15P 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 21:34:53 -07:00
Alex Forencich
026a302c1c Use unified 10G/25G design for ExaNIC X25 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 20:45:47 -07:00
Alex Forencich
5dc38f11b7 Use unified 10G/25G design for Alveo VCU1525 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 20:42:40 -07:00
Alex Forencich
a221adc468 Use unified 10G/25G design for Alveo U50 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 20:40:38 -07:00
Alex Forencich
147435dfe1 Use unified 10G/25G design for Alveo U280 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 20:38:34 -07:00
Alex Forencich
ea80d853ed Use unified 10G/25G design for Alveo U250 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 19:53:21 -07:00
Alex Forencich
0b18633bb1 Use unified 10G/25G design for Alveo U200 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 19:49:25 -07:00
Alex Forencich
489ee73355 Use unified 10G/25G design for VCU118 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 19:02:57 -07:00
Alex Forencich
729c5a61ce Use unified 10G/25G design for ADM-PCIE-9V3 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 18:59:33 -07:00
Alex Forencich
48cbe43fa7 Update Vivado makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 18:48:34 -07:00
Alex Forencich
ed4a26e2cb Update Vivado makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 18:45:01 -07:00
Alex Forencich
b6a9092a9f Update makefiles for Intel devices 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 17:46:34 -07:00
Alex Forencich
c4376c8674 Update XDC files 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-13 17:12:32 -07:00
Alex Forencich
17443e9366 fpga/mqnic: Separate event and completion write instances 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-10 17:53:03 -07:00
Alex Forencich
bed12ee774 Consolidate CQs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-10 17:52:34 -07:00
Alex Forencich
905e6c6358 Add PTP timestamping tests for 1G MAC 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-08 01:41:35 -07:00
Alex Forencich
9665df8a44 Fix PTP timestamping in 1G MAC 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-08 01:41:14 -07:00
Alex Forencich
265035769a Reorganize queue control registers 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-07 01:19:19 -07:00
Alex Forencich
56c89640e0 scripts: Add mqnic_ddcmd.sh script to control dynamic debug statements 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-07 01:11:37 -07:00
Alex Forencich
fa75b47b7b modules/mqnic: Convert more relatively frequent info-level printk calls to debug-level so they can be selectively enabled via dynamic debug 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-07 01:10:49 -07:00
Joachim Foerster
1d729817a6 modules/mqnic: Turn "TX ring ... full ..." message into netdev-related debug message 
To not overwhelm any logging daemon. Full TX queues can be quite common
depending on a system's context and capabilities. Mostly all the details are not
required anyway in such cases.

To enable such debug messages and have their text turn up in dmesg and logging
daemons, the mqnic module has to be compiled with CPP symbol DEBUG being (`make
DEBUG=yes`) defined, or the kernel in use has to support "Dynamic Debug" [1]. In
the latter case all such debug messages in module mqnic can be enabled with:

echo 'module mqnic +pflmt' | sudo tee /sys/kernel/debug/dynamic_debug/control

To enable just this specific messages, based on its (partial) format:

echo 'format "TX ring %d full" +pflmt' | sudo tee /sys/kernel/debug/dynamic_debug/control

[1] https://www.kernel.org/doc/html/latest/admin-guide/dynamic-debug-howto.html

Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
 2023-07-07 00:30:52 -07:00
Joachim Foerster
6a975f3433 modules/mqnic/Makefile: Define CPP symbol DEBUG when environment variable DEBUG is provided 
Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
 2023-07-07 00:30:52 -07:00
Joachim Foerster
51d5712982 modules/mqnic: Introduce proper error path on failing to allocate RX buffers 
This basically allows the "refilling" of RX buffers to fail. A fail to allocate
RX buffers can occur on bringing a network device up or when changing the number
of RX channels at run-time through `ethtool -L <ndev> rx <num>`.

Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
 2023-07-07 00:30:52 -07:00
Alex Forencich
1f0b6a625c PTP parameter clean-up 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-06 16:46:32 -07:00
Alex Forencich
9dafc3aaee Use internal BYTE_LANES parameter 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-06 16:28:08 -07:00
Alex Forencich
4d2c2071cc modules/mqnic: Fix kernel version ifdef for netif_napi_add 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-03 22:54:34 -07:00
Wesley New
a5e810eedc Minor fixes to getingstarted document 
I have updated the docs with a couple of minor writing fixes
 2023-07-03 22:52:07 -07:00
Alex Forencich
9159425cd8 Use correct payload lengths 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-29 22:18:50 -07:00
Alex Forencich
f705646e3e Pull out header size as a parameter 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-29 15:48:39 -07:00
Alex Forencich
9f1f27bc8b scripts: Perform verbose dumps in test script 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-27 23:35:33 -07:00
Alex Forencich
cc202ce45d utils: Add verbose option to mqnic-dump; hide disabled queues, scheduler state, and zero-valued statistics counters by default 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-27 23:31:28 -07:00
Alex Forencich
82df10a356 modules/mqnic: Add missing priv reference 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-27 00:04:09 -07:00
Alex Forencich
6887a4a004 fpga/mqnic/KR260: fix symlink 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-26 15:20:53 -07:00
Ulrich Langenbach
21f5a758c9 modules/mqnic: use unsigned short for I2C addresses 
the i2c_client defines i2c addresses as unsigned short so we follow
this style
 2023-06-26 12:10:27 -07:00
Ulrich Langenbach
b1f14659d9 modules/mqnic: sfp module eeprom i2c address adjustment for full access 
* the optical diagnostics data is provided by the SFP modules
   using another I2C address, which must be set via the I2C client
 2023-06-26 12:10:27 -07:00
Ulrich Langenbach
6bd8ae031f modules/mqnic: fix SFP EEPROM readout to support optical module diagnosis 
* fix offset check for allowing an offset of exactly 256 Bytes
* fix allowing the I2C address of 0x51 to access the optical SFP modules
  diagnosis information, see SFF8472 rev 12.4 p. 8
 2023-06-26 12:10:27 -07:00
Alex Forencich
448fa8eb4c Use SPDX 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-26 11:44:57 -07:00
Alex Forencich
0962811b38 Rename COPYING to LICENSE, use more generic license text 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-26 10:16:45 -07:00
Alex Forencich
9a93cfb5ad fpga/mqnic: Clean up readmes 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-26 00:08:49 -07:00