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Author SHA1 Message Date
Alex Forencich
c6d8983fcd Add wr_done output to DMA RAMs 2021-02-07 23:47:46 -08:00
Alex Forencich
633b47ef7f Update XDC files 2021-02-06 17:14:26 -08:00
Alex Forencich
5d91fde42a Update github actions 2021-01-16 13:40:35 -08:00
Alex Forencich
87a6efe05c Rework sim_build output directory, fix default makefile target 2020-12-29 16:26:48 -08:00
Alex Forencich
44bf507e24 Update readme 2020-12-19 14:59:02 -08:00
Alex Forencich
ba50df774d Add Github Actions regression tests 2020-12-19 14:18:05 -08:00
Alex Forencich
8d7f4b52bf Add test durations 2020-12-19 14:17:47 -08:00
Alex Forencich
0e0e9da047 Add tox.ini 2020-12-19 14:11:23 -08:00
Alex Forencich
a0a5ccc0a4 Add cocotb testbenches 2020-12-19 14:10:57 -08:00
Alex Forencich
7c19cb770d Properly name registers, CQ demux bug fix 2020-12-19 14:09:56 -08:00
Alex Forencich
cabad17552 Migrate example design testbenches to cocotb 2020-12-18 22:10:32 -08:00
Alex Forencich
99e91c4d90 Fix pointer handling issue in PCIe AXI DMA write module 2020-12-18 18:37:53 -08:00
Alex Forencich
f567db764b Rewrite 4K address boundary crossing checks 2020-11-11 23:54:39 -08:00
Alex Forencich
5546e40812 Fix user_clk_frequency setting in testbenches 2020-10-12 23:05:28 -07:00
Alex Forencich
d22d3e8bd1 Update VCU118 XDC 2020-10-06 00:40:16 -07:00
Alex Forencich
8f8cb39157 Update flash programming configuration for ExaNIC X10 and X25 2020-10-03 15:26:56 -07:00
Alex Forencich
10a6797d27 Update VCU108 XDC 2020-10-02 20:49:23 -07:00
Alex Forencich
bbe94fd0d3 Fix flash programming commands for VCU108 2020-10-01 00:50:31 -07:00
Alex Forencich
f3c8e47ccc Fix bitstream config for VCU1525 2020-09-30 23:50:03 -07:00
Alex Forencich
3ce28df7e0 Update flash programming commands 2020-09-29 18:28:38 -07:00
Alex Forencich
c04ba2de2e Fix flash settings 2020-09-29 17:30:42 -07:00
Alex Forencich
a2685a102b Update LED driver timing constraints 2020-09-28 17:24:24 -07:00
Alex Forencich
1f93608527 Add fb2CG flash programming commands 2020-09-27 01:47:00 -07:00
Alex Forencich
44955d2010 Make DMA RAM module synchronous and add async variant for improved RAM inference 2020-09-25 21:49:07 -07:00
Alex Forencich
ef2f01bd9f Update XDC 2020-09-23 14:24:42 -07:00
Alex Forencich
4ae9ec818c Add timing constraints for LED driver 2020-09-22 22:13:54 -07:00
Alex Forencich
c7594c77ab Add fb2CG AXI example design 2020-09-20 01:17:52 -07:00
Alex Forencich
722222a01c Add AU250 AXI example design 2020-09-18 14:51:35 -07:00
Alex Forencich
0080f631c6 Add AU200 AXI example design 2020-09-18 14:51:24 -07:00
Alex Forencich
d7f96eb104 Rewrite priority encoder to remove recusive construction 2020-08-17 18:30:40 -07:00
Alex Forencich
fed4c93b9c Update XDC 2020-08-06 22:06:16 -07:00
Alex Forencich
1e75c3cc70 Fix AXI stream DMA client bug causing dropped writes when widths are the same 2020-08-06 21:32:10 -07:00
Alex Forencich
0d4e9989c8 Fix asserts 2020-08-06 21:31:58 -07:00
Alex Forencich
963f4f8555 Add ZCU106 AXI example design 2020-08-06 18:25:34 -07:00
Alex Forencich
b79ddf5ebd Update makefiles 2020-08-06 18:22:30 -07:00
Alex Forencich
8045992eb6 Remove extraneous code 2020-07-27 22:29:04 -07:00
Alex Forencich
1f523f0bb4 Remove unused reg 2020-07-26 21:39:10 -07:00
Alex Forencich
dd97d2d749 Minor refactoring 2020-07-25 22:09:30 -07:00
Alex Forencich
dc48d86b99 Improve BAR initialization 2020-07-24 22:54:55 -07:00
Alex Forencich
65fd5ef947 Fix AU50 XDC file 2020-07-23 22:36:00 -07:00
Alex Forencich
56dbcb8274 Add AU50 AXI example design 2020-07-17 00:04:13 -07:00
Alex Forencich
d3a1c903d3 XDC clean up 2020-07-13 23:58:45 -07:00
Alex Forencich
5dbb771958 Add AU280 AXI example design 2020-07-12 11:42:48 -07:00
Alex Forencich
ebae4e436d Update AXI simulation model 2020-07-02 21:28:35 -07:00
Alex Forencich
281e1a2156 Convert to TCL IP 2020-07-01 23:53:58 -07:00
Alex Forencich
d6ad22d435 Add DMA block diagram 2020-05-07 12:36:37 -07:00
Alex Forencich
6e974aca27 Driver update for Linux kernel API change 2020-03-26 16:12:56 -07:00
Alex Forencich
566dfa07e7 Read DMA timing optimizations 2020-03-26 14:34:48 -07:00
Alex Forencich
08d92fd138 Add pipeline stage for memory write generation to improve completion handling throughput 2020-03-24 21:58:48 -07:00
Alex Forencich
f8ce39c585 Timing optimization 2020-03-24 19:41:02 -07:00