Alex Forencich
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a5519cd607
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Default to US+ configuration
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2021-08-31 18:57:32 -07:00 |
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Alex Forencich
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bdbdc11841
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Initial commit of core logic
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2021-08-31 18:42:19 -07:00 |
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Alex Forencich
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9731ea5188
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Add new PTP subsystem
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2021-08-31 01:39:19 -07:00 |
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Alex Forencich
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cef2602efe
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Reorganize address space to place port registers in interface register space
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2021-08-30 01:29:25 -07:00 |
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Alex Forencich
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d46cb16dbf
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Add scheduler block
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2021-08-30 01:28:55 -07:00 |
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Alex Forencich
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454d237ab2
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Rename parameter
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2021-08-30 01:27:53 -07:00 |
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Alex Forencich
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34150323df
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Remove obsolete packet table size parameters
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2021-08-20 18:15:06 -07:00 |
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Alex Forencich
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a19474f9dd
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Use AXI lite crossbar
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2021-08-11 01:31:34 -07:00 |
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Alex Forencich
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e0e34a9f0d
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Update designs for PCIe module changes
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2021-08-02 23:04:52 -07:00 |
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Alex Forencich
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c926fd2ca1
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Remove extraneous imports
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2021-06-28 22:35:22 -07:00 |
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minseongg
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9af504a6c0
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Update cmac_pad testbench
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2021-06-28 22:33:57 -07:00 |
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minseongg
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8db2faddc6
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Update cmac_pad testbench
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2021-06-28 22:33:57 -07:00 |
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minseongg
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dc5c8232f9
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Add cmac_pad testbench
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2021-06-28 22:33:57 -07:00 |
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Alex Forencich
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0a7f1ccbbe
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Remove string parameters
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2021-06-02 18:18:23 -07:00 |
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Alex Forencich
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15cb21dbd1
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Reorganize timing constraints
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2021-05-20 15:24:01 -07:00 |
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Alex Forencich
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32abea89fa
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Update testbenches
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2021-03-06 20:30:25 -08:00 |
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Alex Forencich
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a3c104f7dd
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Connect write done signals
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2021-02-24 15:07:26 -08:00 |
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Alex Forencich
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c0c2f933c0
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Rework sim_build output directory, fix default makefile target
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2020-12-29 17:28:53 -08:00 |
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Alex Forencich
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0c0fdc479b
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Update testbenches for async send/recv
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2020-12-18 17:40:36 -08:00 |
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Alex Forencich
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b5ee772761
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Migrate test infrastructure to cocotb
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2020-12-15 16:52:20 -08:00 |
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Alex Forencich
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3003b3228d
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Fix backpressure bug in TX checksum module
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2020-12-12 21:51:54 -08:00 |
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Alex Forencich
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91edbbf3dc
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Rename port and interface modules
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2020-11-26 15:05:59 -08:00 |
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Alex Forencich
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0d1617c05c
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Update DMA RAM instances
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2020-09-25 21:51:31 -07:00 |
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Alex Forencich
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a37d9b3465
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New transceiver control reigster definitions
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2020-09-19 17:25:58 -07:00 |
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Alex Forencich
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3284ec3848
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New I2C register definitions
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2020-09-19 17:25:58 -07:00 |
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Alex Forencich
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cbaffeeac7
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Limit RX DMA size to configured MTU size
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2020-08-25 18:48:17 -07:00 |
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Alex Forencich
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495178e1dc
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Fix mask
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2020-07-28 18:30:52 -07:00 |
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Alex Forencich
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4e958096b2
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Update driver model to set MTU registers
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2020-05-01 19:19:56 -07:00 |
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Alex Forencich
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ae775a9386
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Rewrite RX buffer management
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2020-05-01 19:00:58 -07:00 |
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Alex Forencich
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8b535e54ac
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Add MTU registers
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2020-05-01 18:55:01 -07:00 |
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Alex Forencich
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ca0cbf4d93
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Update parameters
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2020-05-01 17:22:21 -07:00 |
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Alex Forencich
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1f76606667
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Move TDMA registers
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2020-05-01 16:55:57 -07:00 |
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Alex Forencich
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ded213460d
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Rewrite TX buffer management
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2020-05-01 14:29:52 -07:00 |
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Alex Forencich
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1c7b7937e5
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Limit in-flight descriptor requests in TX engine
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2020-04-30 23:37:41 -07:00 |
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Alex Forencich
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45ec6657b1
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Limit in-flight descriptor requests in RX engine
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2020-04-30 23:29:43 -07:00 |
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Alex Forencich
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31cec8d0c1
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Fix cmac_pad frame truncation bug
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2020-04-22 23:23:34 -07:00 |
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Alex Forencich
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9e64d19ea5
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Use scatter descriptor blocks in driver model
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2020-04-21 01:04:07 -07:00 |
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Alex Forencich
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2c6e9673f7
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Add log_desc_block_size ring parameter in driver model
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2020-04-21 00:58:12 -07:00 |
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Alex Forencich
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e14cfa0a58
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Update port and interface modules
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2020-04-20 21:25:21 -07:00 |
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Alex Forencich
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7087a595e9
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Update RX and TX engines to support descriptor blocks
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2020-04-20 21:24:25 -07:00 |
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Alex Forencich
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0fb60d718d
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Add log desc block size to desc_fetch module
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2020-04-20 21:01:55 -07:00 |
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Alex Forencich
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d0cf549057
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Add log desc block size field to queue manager
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2020-04-20 20:45:10 -07:00 |
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Alex Forencich
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50af74aa88
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Change QUEUE_LOG_SIZE_WIDTH to LOG_QUEUE_SIZE_WIDTH
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2020-04-20 18:43:26 -07:00 |
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Alex Forencich
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a196cd227c
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Enable bus mastering and MSI in driver model
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2020-03-12 15:32:08 -07:00 |
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Alex Forencich
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457f4d7f3f
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Use configured ring stride
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2020-03-12 15:28:00 -07:00 |
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Alex Forencich
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0c32192226
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Use constants instead of magic numbers
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2020-03-12 15:08:20 -07:00 |
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Alex Forencich
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1216f7a76e
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Offset packet start by 10 bytes to match Linux kernel skb alignment
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2020-03-08 21:56:08 -07:00 |
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Alex Forencich
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23aef37aff
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Rewrite resets
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2020-03-08 16:56:06 -07:00 |
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Alex Forencich
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248a0b4f93
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Convert descriptor to DMA operation without storing in table
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2020-03-08 00:22:55 -08:00 |
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Alex Forencich
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f7a1a7ef95
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Add descriptor FIFOs
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2020-03-07 22:28:59 -08:00 |
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