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Author	SHA1	Message	Date
Alex Forencich	892ee84bff	Delay command until write is acknowledged	2021-05-31 01:32:02 -07:00
Alex Forencich	3579310447	Clear active bit	2021-05-31 01:31:30 -07:00
Alex Forencich	e32f65f563	Update test durations	2021-05-30 12:39:49 -07:00
Alex Forencich	5d9c982cd4	Add switch testbenches	2021-05-30 12:33:29 -07:00
Alex Forencich	34d5a4fed5	Add wrapper generator for RAM switch	2021-05-30 12:32:26 -07:00
Alex Forencich	9417d5f749	Use cocotb.top	2021-05-30 12:32:02 -07:00
Alex Forencich	16b174b490	Print addressing configuration	2021-05-30 12:19:01 -07:00
Alex Forencich	e3183862bb	tkeep always active inside RAM switch	2021-05-30 12:12:10 -07:00
Alex Forencich	56a3b8fe92	Fix indexed part select error in degenerate case when M_COUNT = 1	2021-05-30 12:11:46 -07:00
Alex Forencich	8e5c4874eb	Fix switch wrapper parameters	2021-05-30 12:10:04 -07:00
Alex Forencich	c1bfa8cc41	Add tuser assert tests	2021-05-25 00:55:59 -07:00
Alex Forencich	a7905ed681	Add stress tests	2021-05-25 00:31:20 -07:00
Alex Forencich	a7ebfdcebb	Add arbitration test	2021-05-25 00:13:32 -07:00
Alex Forencich	15cb21dbd1	Reorganize timing constraints	2021-05-20 15:24:01 -07:00
Alex Forencich	5ebc741ffe	merged changes in axi	2021-05-20 15:17:25 -07:00
Alex Forencich	955fdbf391	merged changes in pcie	2021-05-20 15:17:19 -07:00
Alex Forencich	9c4012f58d	Reorganize timing constraints	2021-05-20 15:15:51 -07:00
Alex Forencich	892aa58004	merged changes in eth	2021-05-20 15:13:16 -07:00
Alex Forencich	b09e01ba48	Update S10MX SDC	2021-05-19 21:57:48 -07:00
Alex Forencich	9df253aa59	Update readme	2021-05-19 21:57:33 -07:00
Alex Forencich	cee82cb695	Add Stratix 10 DX 10G example design	2021-05-19 21:00:54 -07:00
Alex Forencich	13c1bbe79a	Update S10MX QSF	2021-05-19 16:48:58 -07:00
Alex Forencich	1a3c68812f	Update readme	2021-05-18 22:33:01 -07:00
Alex Forencich	0d21ea80ea	Update readme	2021-05-18 22:16:50 -07:00
Alex Forencich	0c493c4ba1	Update readme	2021-05-18 22:11:32 -07:00
Alex Forencich	28686fb115	Update readme	2021-05-18 22:05:44 -07:00
Alex Forencich	20c7967715	Update readme	2021-05-18 19:16:48 -07:00
Alex Forencich	bf6fddd1db	Add Stratix 10 MX 10G example design	2021-05-18 19:16:30 -07:00
Alex Forencich	40265a3e1c	Add timing constraints for Quartus Prime Pro	2021-05-18 18:30:33 -07:00
Alex Forencich	7751aba8da	Reorganize timing constraints	2021-05-18 16:15:41 -07:00
Alex Forencich	f236e7dff1	merged changes in axis	2021-05-18 16:03:37 -07:00
Alex Forencich	b7f3faa628	Add timing constraints for Quartus Prime Pro	2021-05-18 16:02:36 -07:00
Alex Forencich	e9f7723312	Reorganize timing constraints	2021-05-16 23:28:00 -07:00
Alex Forencich	5e1329a992	Rework PHY bitslip timing	2021-05-05 00:35:43 -07:00
Alex Forencich	c021d01c26	Update example design readmes	2021-05-04 15:48:12 -07:00
Alex Forencich	7b2a0a1aed	Update testbenches	2021-04-28 20:54:44 -07:00
Alex Forencich	1a046d8e82	Update testbenches	2021-04-15 23:30:14 -07:00
Alex Forencich	314ea7dbf9	Update readme	2021-04-12 22:55:49 -07:00
Alex Forencich	a45c36e802	Update testbenches	2021-04-12 22:55:38 -07:00
Alex Forencich	77ff92f02b	Avoid sampling own outputs	2021-04-05 20:38:05 -07:00
Alex Forencich	244f136ca7	Remove travis-ci	2021-04-03 17:09:12 -07:00
Alex Forencich	b56bc11598	Update readme	2021-04-03 17:00:18 -07:00
Alex Forencich	397a253584	Add Github Actions regression testing	2021-04-03 16:57:14 -07:00
Alex Forencich	c884efc1f3	Add test durations for pytest-split	2021-04-03 16:56:54 -07:00
Alex Forencich	74c1014671	Add cocotb testbenches	2021-04-03 16:53:08 -07:00
Alex Forencich	17ba806687	Add tox and pytest configuration	2021-04-03 16:36:46 -07:00
Alex Forencich	9d99ec0096	Update wrapper generators	2021-04-03 16:34:42 -07:00
Alex Forencich	3df18fafdd	Use nonblocking assignment	2021-04-03 16:33:45 -07:00
Alex Forencich	0916fb6686	Enable PTP on NetFPGA SUME	2021-04-01 21:58:32 -07:00
Alex Forencich	1bb5d8ab56	Add PTP support at 100G on VCU118	2021-04-01 18:02:58 -07:00