92 Commits

Author	SHA1	Message	Date
Alex Forencich	16fec34ddc	Default FIFO size at least 2 MTU (3000 bytes)	2015-05-08 01:44:55 -07:00
Alex Forencich	00a87b26b3	Add FIFO wrapper for 10G MAC module	2015-05-08 00:07:09 -07:00
Alex Forencich	bf349b16ba	Add 10G MAC module	2015-05-08 00:05:21 -07:00
Alex Forencich	73bebaba46	Add FIFO wrapper for gigabit MAC module	2015-05-07 23:45:30 -07:00
Alex Forencich	3a180bd24f	Improve error signal handling	2015-05-07 19:08:16 -07:00
Alex Forencich	0be84e3b03	Write to _next instead of _reg in async block	2015-05-04 01:17:39 -07:00
Alex Forencich	71511b3671	Remove unused register	2015-04-20 23:37:57 -07:00
Alex Forencich	db6a6e23f5	Add 64 bit Ethernet FCS checker	2015-03-22 01:05:57 -07:00
Alex Forencich	51b5335318	Remove z from default states for FSM inference	2015-03-09 02:38:39 -07:00
Alex Forencich	d73b296903	Properly handle short packets	2015-03-04 13:06:29 -08:00
Alex Forencich	17ad08e412	Add 64-bit Ethernet FCS inserter	2015-03-04 00:33:26 -08:00
Alex Forencich	263891b3f6	Make sure all paths set state_next	2015-03-04 00:31:41 -08:00
Alex Forencich	23fa1f1207	Handle tlast on first cycle	2015-03-03 21:46:02 -08:00
Alex Forencich	d3e30d0a73	Fix padding bug	2015-02-28 23:09:41 -08:00
Alex Forencich	14e71d568d	Improve classifier logic by registering payload select signals	2015-02-28 19:14:22 -08:00
Alex Forencich	d57c857d88	Put PHY interface registers into IOBs for timing	2015-02-28 18:24:20 -08:00
Alex Forencich	7532915bb7	Add GMII PHY interface module	2015-02-28 01:11:03 -08:00
Alex Forencich	6b4dd02946	Resolve multiple driver issue	2015-02-28 00:43:27 -08:00
Alex Forencich	b892fd1172	Add UDP complete module and testbench	2015-02-26 22:57:24 -08:00
Alex Forencich	635f05e9c6	Remove udp_ip_protocol input	2015-02-26 22:37:40 -08:00
Alex Forencich	10108d5d1a	Add 2 port IP mux components	2015-02-26 22:05:07 -08:00
Alex Forencich	d34aaf784d	Add UDP modules	2015-02-26 21:19:26 -08:00
Alex Forencich	6dee616834	Add gigabit MAC module	2015-02-26 19:16:08 -08:00
Alex Forencich	bfe6c37ca9	Add ethernet FCS inserter and checker	2015-02-26 19:00:33 -08:00
Alex Forencich	da04654196	Add Ethernet FCS calculator modules	2015-02-26 16:11:04 -08:00
Alex Forencich	c25c35d198	Add Ethernet CRC modules	2015-02-25 14:40:26 -08:00
Alex Forencich	4a228f06c5	Add IP complete module and testbench	2014-11-21 00:03:08 -08:00
Alex Forencich	9bf6f01649	Add 2 port Ethernet mux components	2014-11-21 00:02:20 -08:00
Alex Forencich	96b6e7ca96	Ignore transient requests	2014-11-21 00:00:27 -08:00
Alex Forencich	d483ebb8da	Drop arp request earlier	2014-11-20 23:59:54 -08:00
Alex Forencich	2ae3581144	Add ARP module and testbench	2014-11-20 22:55:28 -08:00
Alex Forencich	7fdb7b4f35	Add ARP cache module	2014-11-20 22:54:08 -08:00
Alex Forencich	f35ecece83	Initialize tkeep properly	2014-11-20 22:52:52 -08:00
Alex Forencich	fc6ccd97fb	Rework IP modules	2014-11-20 12:11:11 -08:00
Alex Forencich	64f6488bf1	Add UDP demux module and testbench	2014-11-18 15:17:50 -08:00
Alex Forencich	1b69fc5eed	Add UDP arbitrated mux and testbench	2014-11-18 14:53:31 -08:00
Alex Forencich	a5d68fcff9	Add UDP mux module and testbench	2014-11-18 14:41:48 -08:00
Alex Forencich	348a347616	Add IP demux and testbench	2014-11-18 12:36:12 -08:00
Alex Forencich	fbca60e65e	Add IP arbitrated mux and testbench	2014-11-18 11:48:11 -08:00
Alex Forencich	f6fcec08f3	Add IP mux module and testbench	2014-11-18 11:27:34 -08:00
Alex Forencich	4db581ae3c	Add ethernet demux module and testbench	2014-11-17 21:52:49 -08:00
Alex Forencich	885d847514	Rework header ready set	2014-11-17 19:27:45 -08:00
Alex Forencich	59952bd8cf	Do not accept new frame until header is read	2014-11-17 18:10:35 -08:00
Alex Forencich	4d1180d74c	Reverse priority in arbitrated mux	2014-11-16 02:20:44 -08:00
Alex Forencich	f1d075d974	Add enable signal	2014-11-16 02:13:43 -08:00
Alex Forencich	c90d5141ac	Add ethernet arbitrated mux module and testbench	2014-11-14 22:11:49 -08:00
Alex Forencich	9bee01e74c	Add ethernet mux and testbench	2014-11-14 17:48:51 -08:00
Alex Forencich	96c6fcd144	Remove AXI stream components	2014-11-05 16:59:59 -08:00
Alex Forencich	588c2742e8	Separate out input mux in AXI frame joiner	2014-10-28 01:55:42 -07:00
Alex Forencich	0f62d31fef	Rework ARP datapath modules to separate output register	2014-10-28 01:55:36 -07:00