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361 Commits 1 Branch 0 Tags
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146 Commits

Author SHA1 Message Date
Alex Forencich
cb6b15cae0 Reset error signal monitor 2021-10-03 12:17:57 -07:00
Alex Forencich
85b8231abf Add IO operations to bad ops test for pcie_axil_master_minimal 2021-10-03 11:47:45 -07:00
Alex Forencich
bb74bdf2f7 Update pcie_axil_master module to support arbitrary memory operations 2021-10-03 11:46:55 -07:00
Alex Forencich
eea6b66f3f Add PCIe AXI master modules and testbenches 2021-10-02 00:59:18 -07:00
Alex Forencich
2984b5b09d Copy pcie_axil_master as pcie_axil_master_minimal 2021-09-30 22:38:28 -07:00
Alex Forencich
f2f19f7174 Update terminology, use byte_lanes instead of byte_width 2021-09-25 22:52:19 -07:00
Alex Forencich
bc8715decc Hold read completions until pending writes complete 2021-09-25 00:46:55 -07:00
Alex Forencich
85391d2b9b Compare all fields 2021-08-20 14:10:03 -07:00
Alex Forencich
7810b3c99e Connect RQ sequence number ports in pcie_us_if testbench 2021-08-11 19:53:28 -07:00
Alex Forencich
7fed6876a3 Init seq to 0 2021-08-11 19:52:47 -07:00
Alex Forencich
ac96ae97d3 Add flow control signals to pcie_us_if 2021-08-11 19:37:51 -07:00
Alex Forencich
f8f95a214b Set completer ID in testbench 2021-08-04 17:08:25 -07:00
Alex Forencich
836d14bad6 Add PCIe interface shim for Xilinx UltraScale 2021-08-04 01:03:31 -07:00
Alex Forencich
b95f030408 Add PCIe DMA interface modules and testbenches 2021-08-04 01:02:48 -07:00
Alex Forencich
1a5e96d0fd Add PCIe AXI lite master module and testbench 2021-08-04 01:01:22 -07:00
Alex Forencich
623cc1ae8d Add generic PCIe interface model 2021-08-03 22:33:23 -07:00
Alex Forencich
36ec7aaa16 Add error reporting to DMA modules 2021-08-02 17:24:00 -07:00
Alex Forencich
dad637bd00 Properly handle zero-length DMA operations 2021-07-25 01:36:40 -07:00
Alex Forencich
59c026b1b8 Fix parameters 2021-07-24 02:02:30 -07:00
Alex Forencich
3e03b20bc7 Properly handle zero-length PCIe read and write operations 2021-07-24 01:13:25 -07:00
Alex Forencich
1a046d8e82 Update testbenches 2021-04-15 23:30:14 -07:00
Alex Forencich
77ff92f02b Avoid sampling own outputs 2021-04-05 20:38:05 -07:00
Alex Forencich
04cbbeb879 Add bus objects for DMA RAM 2021-03-17 22:12:42 -07:00
Alex Forencich
bdfeaa84ca Update testbenches 2021-03-06 20:06:23 -08:00
Alex Forencich
670dfa0d11 Fix pcie_us_axi_dma_wr testbench file list 2021-02-28 19:50:45 -08:00
Alex Forencich
5715e12d41 Remove tag manager module 2021-02-28 19:37:16 -08:00
Alex Forencich
438a4fdcc9 Use FIFOs for PCIe tag management in PCIe read DMA modules 2021-02-28 19:34:24 -08:00
Alex Forencich
062495b780 Remove redundant parameter PCIE_EXT_TAG_ENABLE 2021-02-25 18:20:08 -08:00
Alex Forencich
8294eecd65 Remove redundant parameter PCIE_TAG_WIDTH 2021-02-25 18:10:59 -08:00
Alex Forencich
6fb2eb6b4e Remove unnecessary delays from testbenches 2021-02-24 13:50:45 -08:00
Alex Forencich
070689692d Add wr_done signal to RAM model and placeholders to DMA components 2021-02-24 13:47:53 -08:00
Alex Forencich
742ef1c272 Add same-width test cases to DMA clients 2021-02-16 01:26:05 -08:00
Alex Forencich
93496729f3 Update testbench 2021-02-12 16:59:13 -08:00
Alex Forencich
5f7697178b Remove await ReadOnly 2021-02-10 18:42:32 -08:00
Alex Forencich
87a6efe05c Rework sim_build output directory, fix default makefile target 2020-12-29 16:26:48 -08:00
Alex Forencich
a0a5ccc0a4 Add cocotb testbenches 2020-12-19 14:10:57 -08:00
Alex Forencich
dc48d86b99 Improve BAR initialization 2020-07-24 22:54:55 -07:00
Alex Forencich
ebae4e436d Update AXI simulation model 2020-07-02 21:28:35 -07:00
Alex Forencich
060320010d Don't configure MSI if already configured 2020-03-02 21:16:09 -08:00
Alex Forencich
a6d64bbcbb Remove extraneous character 2019-12-07 14:36:32 -08:00
Alex Forencich
d561195dc8 Add get_data_credits to TLP 2019-12-07 00:54:16 -08:00
Alex Forencich
7567db1818 Add credit-based flow control to DMA cores 2019-12-06 23:24:36 -08:00
Alex Forencich
00858212c6 Placeholder values for flow control credit outputs 2019-12-06 19:16:05 -08:00
Alex Forencich
8985c6dbf3 Add RQ sequence number inputs, operation table, TX_LIMIT parameter to ultrascale write DMA modules 2019-12-03 15:46:36 -08:00
Alex Forencich
a7be8e8f87 Clear the sequence number valid bits 2019-11-27 16:43:15 -08:00
Alex Forencich
4c8fcef230 Add RQ sequence number inputs, TX_LIMIT parameter to ultrascale read DMA modules 2019-11-26 16:30:30 -08:00
Alex Forencich
c5a0d05b47 Add OP_TABLE_SIZE parameter to testbenches 2019-11-26 00:00:49 -08:00
Alex Forencich
e7bd0a62f1 Implement RQ sequence numbers in Ultrascale models 2019-11-25 18:07:49 -08:00
Alex Forencich
bbcdcc17bc Rename OP_TAG_WIDTH to OP_TABLE_SIZE 2019-11-25 14:59:53 -08:00
Alex Forencich
176e1159a3 Update python parameter computation to match verilog clog2 2019-11-24 00:01:33 -08:00