Alex Forencich
|
2a7d0e0947
|
Use new PTP time distribution subsystem
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2023-11-07 21:57:07 -08:00 |
|
Alex Forencich
|
d9e4b82f7a
|
fpga: PTP sample clock is no longer optional, so remove PTP_USE_SAMPLE_CLOCK parameter
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2023-09-24 13:52:06 -07:00 |
|
Alex Forencich
|
448fa8eb4c
|
Use SPDX
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2023-06-26 11:44:57 -07:00 |
|
Alex Forencich
|
ef5b2449dc
|
Add stretched PTP PPS output
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-07-18 22:25:58 -07:00 |
|
Alex Forencich
|
835f0d38f0
|
Update PTP subsystem to use separate clock for improved stability
Signed-off-by: Alex Forencich <alex@alexforencich.com>
|
2022-05-06 17:46:16 -07:00 |
|
Alex Forencich
|
dfae34ed25
|
Pass through PTP pipelining settings
|
2022-03-28 00:50:29 -07:00 |
|
Alex Forencich
|
ce21774f06
|
Register space reorganization
|
2021-12-29 22:31:46 -08:00 |
|
Alex Forencich
|
7ac4797336
|
Add default_nettype none and resetall directives
|
2021-10-20 21:53:39 -07:00 |
|
Alex Forencich
|
9731ea5188
|
Add new PTP subsystem
|
2021-08-31 01:39:19 -07:00 |
|