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Commit Graph

213 Commits

Author SHA1 Message Date
Alex Forencich
cc6348653d Add TDMA variants 2021-09-13 17:19:50 -07:00
Alex Forencich
b1596751cf Update NetFPGA SUME design 2021-09-13 01:30:36 -07:00
Alex Forencich
f66f4d7cce Update VCU118 designs 2021-09-13 00:09:23 -07:00
Alex Forencich
bfea350194 Update VCU108 design 2021-09-12 23:17:50 -07:00
Alex Forencich
58a2dbd734 Update ZCU106 design 2021-09-12 23:17:01 -07:00
Alex Forencich
3f8becb186 Update ExaNIC X10 design 2021-09-12 21:56:33 -07:00
Alex Forencich
a18eced17f Update ExaNIC X25 design 2021-09-12 12:40:39 -07:00
Alex Forencich
49a2b6462f Update ADM-PCIE-9V3 designs 2021-09-11 23:22:08 -07:00
Alex Forencich
200ef77b09 Update VCU1525 designs 2021-09-11 20:07:32 -07:00
Alex Forencich
d7e9e91644 Fix FIFO size parameter defaults 2021-09-11 17:42:24 -07:00
Alex Forencich
26fdddb3ae Update Alveo U250 designs 2021-09-11 01:27:23 -07:00
Alex Forencich
ed418f101a Update Alveo U200 designs 2021-09-10 23:40:53 -07:00
Alex Forencich
9b1188860b Update Alveo U50 designs 2021-09-10 19:07:55 -07:00
Alex Forencich
079ad5ec37 Add pblock for 10G MACs 2021-09-10 18:52:46 -07:00
Alex Forencich
9ee5463b92 Remove blank line 2021-09-10 18:52:22 -07:00
Alex Forencich
6a44a59b2c Move LED assignments 2021-09-10 10:53:41 -07:00
Alex Forencich
ada43236d9 Fix alignment 2021-09-09 23:17:52 -07:00
Alex Forencich
c56f6d717b Fix IDs 2021-09-09 22:05:27 -07:00
Alex Forencich
c92dbfe7ed Update file lists 2021-09-09 21:52:16 -07:00
Alex Forencich
fcf4bc007f Update Alveo U280 designs 2021-09-09 18:09:08 -07:00
Alex Forencich
d24c53a2ad Add application section 2021-09-09 16:01:26 -07:00
Alex Forencich
97e3daa36c Extract information from design instead of env vars 2021-09-08 16:44:58 -07:00
Alex Forencich
c920272e84 Use interface address widths directly instead of BAR size parameters 2021-09-08 14:51:18 -07:00
Alex Forencich
cef144e376 Expose DMA_LEN_WIDTH and DMA_TAG_WIDTH parameters 2021-09-08 00:18:11 -07:00
Alex Forencich
bdd2312ecc More descriptive parameter and signal names for AXI lite control connections 2021-09-07 01:35:15 -07:00
Alex Forencich
8cf16c182b More descriptive parameter names (SYNC instead of INT) 2021-09-07 01:29:35 -07:00
Alex Forencich
15dec9458a Add statistics counter subsystem 2021-09-05 23:03:22 -07:00
Alex Forencich
ef00d5ccfd Add parameters for FIFO output pipeline register depth 2021-09-02 14:45:18 -07:00
Alex Forencich
600001b894 Update placement constraints 2021-09-01 16:10:39 -07:00
Alex Forencich
09a10fc3ca Fix MAC clock period parameters 2021-09-01 02:06:25 -07:00
Alex Forencich
b630fdaeb0 Fix QSFP mapping comments 2021-09-01 02:01:14 -07:00
Alex Forencich
9295184e19 Fix signal width parametrization 2021-09-01 01:59:42 -07:00
Alex Forencich
fc835e0ab6 Use TX PTP CDC for both RX and TX due to synchronous clocking 2021-08-31 23:38:24 -07:00
Alex Forencich
82d0770daf Remove unused constraints file 2021-08-31 23:33:00 -07:00
Alex Forencich
c3d498101b Clarify widths 2021-08-31 23:32:42 -07:00
Alex Forencich
37a558e4f6 Add pipeline FIFOs 2021-08-31 22:30:45 -07:00
Alex Forencich
1fc991fc05 Convert fb2CG designs to use common core modules 2021-08-31 21:33:49 -07:00
Alex Forencich
bd3fa6abfd Update vivado.mk 2021-08-31 20:03:33 -07:00
Alex Forencich
d46cb16dbf Add scheduler block 2021-08-30 01:28:55 -07:00
Alex Forencich
f71d28c6d8 Normalize RAM size and max frame size 2021-08-20 21:18:44 -07:00
Alex Forencich
4ceefa376a Normalize FIFO size to 32K 2021-08-20 21:17:41 -07:00
Alex Forencich
34150323df Remove obsolete packet table size parameters 2021-08-20 18:15:06 -07:00
Alex Forencich
84e19ca305 Update file lists 2021-08-16 18:12:19 -07:00
Alex Forencich
38f766646b Connect flow control signals to pcie_us_if 2021-08-12 00:05:43 -07:00
Alex Forencich
6517d43ee7 Add missing connection 2021-08-11 23:52:44 -07:00
Alex Forencich
a19474f9dd Use AXI lite crossbar 2021-08-11 01:31:34 -07:00
Alex Forencich
3e489fde27 Fix instance name 2021-08-04 12:37:13 -07:00
Alex Forencich
49aa27d1c5 Add placement constraints for AU50 2021-08-04 01:23:22 -07:00
Alex Forencich
0b65a1271a Use new PCIe DMA modules 2021-08-04 01:20:57 -07:00
Alex Forencich
e0e34a9f0d Update designs for PCIe module changes 2021-08-02 23:04:52 -07:00