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Author SHA1 Message Date
Alex Forencich
2074d7212f Fix assignment type 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-22 17:08:16 -07:00
Alex Forencich
b0a4d75fd9 Remove extraneous code 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-22 01:08:01 -07:00
Alex Forencich
4a32c86f07 Match integrator width to period register width in PTP CDC module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-22 01:07:43 -07:00
Alex Forencich
cf441f004d Rename source sync signals in PTP CDC module for consistency 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-22 01:07:12 -07:00
Alex Forencich
4b1f48ab5b Parameter clean-up in PTP CDC module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-21 16:34:05 -07:00
Alex Forencich
aad30d09a1 Make FNS_WIDTH an internal parameter in PTP CDC module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-21 16:30:29 -07:00
Alex Forencich
98b4fbb56d Remove USE_SAMPLE_CLOCK parameter in PTP CDC module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-18 16:58:02 -07:00
Alex Forencich
060e55b915 Wait for correct PTP CDC instance to lock 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-18 16:39:30 -07:00
Alex Forencich
70ff3e9383 fpga/mqnic: Enable devlink and DSA on petalinux 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-14 19:17:02 -07:00
Alex Forencich
c2d6942233 modules/mqnic: Call devlink_register earlier 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-14 15:24:25 -07:00
Alex Forencich
1e2bcbbb2b modules/mqnic: Add devlink kernel version ifdefs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-13 18:27:57 -07:00
Alex Forencich
54d0165f68 modules/mqnic: Register ports with devlink 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-13 16:40:27 -07:00
Alex Forencich
a9800099e3 modules/mqnic: Add initial devlink support 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-12 11:17:24 -07:00
Alex Forencich
2d975c1e83 modules/mqnic: Store build date as a string 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-12 11:16:10 -07:00
Alex Forencich
cef4100af0 modules/mqnic: Adjust default LFC watermark 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-11 22:58:31 -07:00
Alex Forencich
5e53dd10ea fpga/mqnic: Increase RX FIFO size 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-11 22:47:35 -07:00
Alex Forencich
6b256f82d3 Generate pause frames on TX 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-10 23:22:50 -07:00
Alex Forencich
9963674c61 Add flow control 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-09 19:01:36 -07:00
Alex Forencich
a169578cfd fpga/common/syn: Fix TDMA BER channel timing constraints 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-09 18:58:30 -07:00
Alex Forencich
6e260f3e79 fpga/mqnic: Update modified FIFO modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-07 20:10:48 -07:00
Alex Forencich
57ffccba15 fpga/mqnic: Cleanup 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-07 18:50:55 -07:00
Alex Forencich
719231b878 fpga/mqnic/VCU118: Update VCU118 makefiles 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-07 18:41:15 -07:00
Alex Forencich
e0b31d9b94 fpga/mqnic: Add MAC-related parameters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-07 18:35:42 -07:00
Alex Forencich
31ced63c91 fpga/mqnic: Add missing XGMII parameter connections 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-07 18:30:13 -07:00
Alex Forencich
ebd7cb7ad9 modules/mqnic: Store port references in netdev priv 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-06 21:48:38 -07:00
Alex Forencich
2e387d3630 fpga/mqnic: Ensure class code lookup assistant is disabled in PCIe core instances 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-05 23:44:12 -07:00
Alex Forencich
06226ac777 fpga/mqnic: Fix PCIe subsystem vendor IDs on UltraScale devices 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-04 23:05:25 -07:00
Alex Forencich
7e497db017 fpga/mqnic: Clean up PCIe core instances 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-04 23:04:58 -07:00
Alex Forencich
36576d8981 Update MAC and PHY instances 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-28 17:22:34 -07:00
Alex Forencich
9095e7ae0b merged changes in eth 2023-08-28 12:26:02 -07:00
Alex Forencich
c5af0f726a fpga/mqnic: Use arrays for QSFP pins 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-28 12:21:09 -07:00
Alex Forencich
b316c6764e Use quad wrappers in ExaNIC X25 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 12:44:50 -07:00
Alex Forencich
f9eda00d68 Use quad wrappers in ExaNIC X10 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 12:43:29 -07:00
Alex Forencich
dc58b2447f Use quad wrappers in ZCU102 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 12:42:39 -07:00
Alex Forencich
d5df47d8b0 Use quad wrappers in ZCU106 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 12:42:04 -07:00
Alex Forencich
4618edcd8e Use quad wrappers in VCU108 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 01:15:29 -07:00
Alex Forencich
72de6c653a Use quad wrappers in AU50 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 01:09:00 -07:00
Alex Forencich
66987c8f62 Use quad wrappers in AU280 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 01:08:32 -07:00
Alex Forencich
22f327b35f Use quad wrappers in AU250 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 01:07:30 -07:00
Alex Forencich
65361d157b Use quad wrappers in AU200 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 01:06:28 -07:00
Alex Forencich
bd06e57764 Use quad wrappers in VCU1525 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 01:05:23 -07:00
Alex Forencich
c673ddbc14 Use quad wrappers in fb2CG@KU15P example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 00:37:44 -07:00
Alex Forencich
5d61059488 Use quad wrappers in ADM-PCIE-9V3 example design 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-26 00:36:39 -07:00
Alex Forencich
1e88ed3d2e Update readme 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-25 23:12:59 -07:00
Alex Forencich
68736d02ae Add 10G/25G design for Arista 7132LB-48Y4C switch 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-25 23:06:49 -07:00
Alex Forencich
351ec79fef Use quad wrappers in VCU118 example designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-25 01:27:53 -07:00
Alex Forencich
75c2cc0acc Use quad wrappers in HTG9200 example designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-25 01:24:26 -07:00
Alex Forencich
aaeeb05ac0 Fix PHY configuration connections 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-25 00:09:38 -07:00
Alex Forencich
fa05d4ff3c Add TX and RX enable inputs to MACs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-24 01:24:33 -07:00
Alex Forencich
88166c1153 modules/mqnic: Drop short frames 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-23 17:50:20 -07:00