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Commit Graph

26 Commits

Author SHA1 Message Date
Alex Forencich
bed12ee774 Consolidate CQs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-10 17:52:34 -07:00
Alex Forencich
448fa8eb4c Use SPDX 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-26 11:44:57 -07:00
Alex Forencich
bb158d568f Add RX indirection table 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-04-10 15:05:32 -07:00
Alex Forencich
efbeecde35 fpga/common: Clean up parameters 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-21 15:19:49 -07:00
Alex Forencich
4b8aaea5c1 fpga/common: Add skid buffer to TX/RX engine DMA descriptor outputs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-09-20 21:50:58 -07:00
Alex Forencich
2bd8350276 Add RX queue mapping module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-04-23 00:12:22 -07:00
Alex Forencich
66708ed6ff Add some more parameter checks 2022-02-14 00:41:28 -08:00
Alex Forencich
335a5e890b Initial implementation of shared interface datapath 2021-12-31 14:33:31 -08:00
Alex Forencich
f8a24d1c46 Add attributes to RAMs for proper synthesis in Quartus 2021-11-06 16:14:22 -07:00
Alex Forencich
7ac4797336 Add default_nettype none and resetall directives 2021-10-20 21:53:39 -07:00
Alex Forencich
e0e34a9f0d Update designs for PCIe module changes 2021-08-02 23:04:52 -07:00
Alex Forencich
cbaffeeac7 Limit RX DMA size to configured MTU size 2020-08-25 18:48:17 -07:00
Alex Forencich
ae775a9386 Rewrite RX buffer management 2020-05-01 19:00:58 -07:00
Alex Forencich
45ec6657b1 Limit in-flight descriptor requests in RX engine 2020-04-30 23:29:43 -07:00
Alex Forencich
7087a595e9 Update RX and TX engines to support descriptor blocks 2020-04-20 21:24:25 -07:00
Alex Forencich
23aef37aff Rewrite resets 2020-03-08 16:56:06 -07:00
Alex Forencich
248a0b4f93 Convert descriptor to DMA operation without storing in table 2020-03-08 00:22:55 -08:00
Alex Forencich
6270278c75 Add RSS support 2019-12-06 14:15:16 -08:00
Alex Forencich
8fa7e40507 Use new DMA subsystem 2019-10-17 16:02:14 -07:00
Alex Forencich
2325966973 Pull out descriptor and completion handling logic 2019-09-23 18:10:35 -07:00
Alex Forencich
7f33bf4982 Update rx_engine to return length 2019-09-02 08:15:07 -07:00
Alex Forencich
ce648698ce Enforce parameter range 2019-09-02 08:13:43 -07:00
Alex Forencich
bcfd665823 Connect queue index field in queue operation response 2019-09-01 08:29:22 -07:00
Alex Forencich
364d835957 Split queue op tag table entry 2019-08-29 19:44:43 -07:00
Alex Forencich
26f6774182 Parameter updates and documentation 2019-07-27 23:47:46 -07:00
Alex Forencich
f94e83e520 Add transmit and receive engines 2019-07-17 16:38:57 -07:00