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Author SHA1 Message Date
Alex Forencich
c95e8f70f2 Update PCIe TLP interface parametrization 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-05 14:31:10 -07:00
Alex Forencich
5595953d5a merged changes in pcie 2022-06-05 14:30:42 -07:00
Alex Forencich
aadcd53c87 Update AXI DMA IF tests 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-05 14:29:16 -07:00
Alex Forencich
7d92722fe8 Clean up testbench parametrization 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-05 14:25:28 -07:00
Alex Forencich
70dc92c24e Rework TLP interface parametrization 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-05 13:27:04 -07:00
Alex Forencich
ee59fc10e0 Update testbenches for new version of cocotbext-pcie 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-05 13:26:27 -07:00
Alex Forencich
a5d7833bd9 Update testbenches for new version of cocotbext-pcie 2022-06-05 00:24:42 -07:00
Alex Forencich
87bf5f2e41 Properly implement zero-length operations in generic interface model 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-04 14:52:54 -07:00
Alex Forencich
21b0f014a5 Switch to MSI-X 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-02 23:58:29 -07:00
Alex Forencich
6cda5f857c merged changes in pcie 2022-06-02 23:36:46 -07:00
Alex Forencich
228d20b3f4 Update example designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-02 23:36:01 -07:00
Alex Forencich
5208b2844c Add MSI-X support to shims 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-02 23:35:34 -07:00
Alex Forencich
2fa0bf3eb0 Add MSI-X module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-02 23:34:15 -07:00
Alex Forencich
ba5188dd93 Update testbenches for new version of cocotbext-pcie 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-06-02 23:33:52 -07:00
Alex Forencich
cc8b9fa9ca Add plotting script 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-31 21:06:32 -07:00
Alex Forencich
628324179e Collect PCIe information and include MAC addresses in test report 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-31 21:05:11 -07:00
Alex Forencich
b50073417d Add MTU settings to scripts 2022-05-31 21:04:22 -07:00
Alex Forencich
dd2853bf40 Update testbenches for latest version of cocotbext-pcie 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-30 13:10:39 -07:00
Alex Forencich
ae55dcc432 Add missing parameter 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-30 13:09:34 -07:00
Joachim Foerster
d6b2a38a92 modules/mqnic: Fix link status monitoring, initialize stored link status on start to "down" 
Assume that the hardware link status is "down" when a netdev is brought "up"
administratively ("ip link set dev ... up"). This way a change of link status is
always occuring, in case hardware link status is indeed still "up" at that point
in time.

Otherwise bringing a netdev administratively "down" and "up" again, while the
hardware was "up" before and stays "up" during the administrative "down" period,
results in no netif_carrier_on() being called, because struct
mqnic_priv::link_status does not change.

Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
 2022-05-30 13:08:10 -07:00
Alex Forencich
4cdb57bfe1 Update module documentation 2022-05-23 21:23:13 -07:00
Joachim Foerster
0d2e794b74 modules/mqnic: Add link status monitoring 
This solution is based on the assumption that, if there are multiple
(mqnic-)ports per (mqnic-)interface, the single netdev, which is currently
associated with one (mqnic-)interface, is assumed to be up, when all ports' TX
and RX status bits are asserted. As soon as one of these bits is deasserted for
any of the involved ports the netdev is assumed to be down.

Module parameter "link_status_poll" specifies the polling interval in
milliseconds. Setting it to 0, disables any form of monitoring. By default we
check once per second, which is a totally arbitrary choice - no special
reasoning.

Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
 2022-05-23 13:59:46 -07:00
Joachim Foerster
db1bb30745 modules/mqnic: Export link status via ethtool 
Makes ethtool show the usual "Link detected" line.

Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
 2022-05-23 13:59:46 -07:00
Joachim Foerster
2697ec93e9 modules/mqnic: Minor, fix warning, when CONFIG_AUXILIARY_BUS is not available 
Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
 2022-05-23 13:59:46 -07:00
Alex Forencich
36e202352b Add NIC test script 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-18 20:04:45 -07:00
Alex Forencich
fe2ff4ce36 Add missing symlink 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-18 19:47:19 -07:00
Alex Forencich
b3c93b5ac7 Fix MAC address EEPROM offsets for Xilinx dev boards 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-18 19:36:12 -07:00
Alex Forencich
5da044826d Add board-level configuration parameter for TDMA BER module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-18 11:25:58 -07:00
Alex Forencich
0c7bdb5635 Add missing QSFP28 control signal connections on AU200 and AU250 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-18 01:30:19 -07:00
Alex Forencich
ed2d34153d Use PHY rx_status signal for link status detection 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-17 00:46:05 -07:00
Alex Forencich
5058b797d2 merged changes in eth 2022-05-16 23:23:27 -07:00
Alex Forencich
85e4f1d8ba Add PHY RX status output for a more reliable link up indication 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 23:22:30 -07:00
Alex Forencich
a855fb3fb6 Use correct sync types 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 23:22:01 -07:00
Alex Forencich
a5934dae60 Add PTP timestamping tests to MACs and related modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 23:21:42 -07:00
Alex Forencich
e06eb07621 Set PTP CDC NS width to 6 in MAC modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 23:20:42 -07:00
Alex Forencich
9012e25211 Fix PTP timestamp capture delay in axis_xgmii_tx_32 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 23:16:24 -07:00
Alex Forencich
7cb15647e7 Better handling of integrator saturation in PTP CDC module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 23:15:31 -07:00
Alex Forencich
d96d5dfba0 Fix clock active detection in PTP CDC module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 23:13:36 -07:00
Alex Forencich
7e5f6a2589 Remove extraneous code 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 18:54:29 -07:00
Alex Forencich
4676296c49 Add block names 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 18:51:27 -07:00
Alex Forencich
77617167fa Fix PTP TS FIFO instantiations 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 17:34:54 -07:00
Alex Forencich
0ad02db4a8 Fix PTP timestamp capture in axis_xgmii_rx_32 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 17:18:02 -07:00
Alex Forencich
af0e15b241 Fix MAC RX PTP timestamp in sideband for axis_baser_rx_64 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 17:14:41 -07:00
Alex Forencich
2b33698f9b Fix alignment 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 13:25:13 -07:00
Alex Forencich
814a51a37c Use 128 KB RX RAM size for 25G designs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 13:24:56 -07:00
Alex Forencich
827cb1ea1d Pipeline arbitration delay in muxes 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-15 19:35:39 -07:00
Alex Forencich
01aa6a885b Rewrite early ready condition 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-15 19:32:28 -07:00
Alex Forencich
a020225304 Rewrite resets 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-15 19:30:14 -07:00
Alex Forencich
42cf40f338 merged changes in pcie 2022-05-15 19:27:48 -07:00
Alex Forencich
d685b0b125 Avoid width mismatch warning 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-15 19:26:10 -07:00