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Author SHA1 Message Date
Alex Forencich
cef144e376 Expose DMA_LEN_WIDTH and DMA_TAG_WIDTH parameters 2021-09-08 00:18:11 -07:00
Alex Forencich
c00a53155d Fix alignment 2021-09-07 01:38:09 -07:00
Alex Forencich
bdd2312ecc More descriptive parameter and signal names for AXI lite control connections 2021-09-07 01:35:15 -07:00
Alex Forencich
8cf16c182b More descriptive parameter names (SYNC instead of INT) 2021-09-07 01:29:35 -07:00
Alex Forencich
15dec9458a Add statistics counter subsystem 2021-09-05 23:03:22 -07:00
Alex Forencich
9ccd43d470 Add statistics collection modules 2021-09-05 18:28:37 -07:00
Alex Forencich
65178395ed merged changes in pcie 2021-09-05 15:43:16 -07:00
Alex Forencich
1321e8e41a Refactor check 2021-09-05 15:30:37 -07:00
Alex Forencich
8a6abc51ed Add statistics outputs to DMA interface 2021-09-05 15:29:56 -07:00
Alex Forencich
5d760851ac Limit queue manager pipelines to a single AXI lite operation 2021-09-05 12:46:56 -07:00
Alex Forencich
ef00d5ccfd Add parameters for FIFO output pipeline register depth 2021-09-02 14:45:18 -07:00
Alex Forencich
f3eeb653d1 Fix test 2021-09-02 00:00:37 -07:00
Alex Forencich
600001b894 Update placement constraints 2021-09-01 16:10:39 -07:00
Alex Forencich
34ae6a9513 merged changes in eth 2021-09-01 16:10:05 -07:00
Alex Forencich
b6f792cc10 merged changes in axis 2021-09-01 15:54:12 -07:00
Alex Forencich
6c234260b2 Fix assignment type 2021-09-01 15:53:15 -07:00
Alex Forencich
de869347cd Register interrupt signal 2021-09-01 13:14:02 -07:00
Alex Forencich
df9523011c Normalize instance names 2021-09-01 02:14:53 -07:00
Alex Forencich
09a10fc3ca Fix MAC clock period parameters 2021-09-01 02:06:25 -07:00
Alex Forencich
b630fdaeb0 Fix QSFP mapping comments 2021-09-01 02:01:14 -07:00
Alex Forencich
9295184e19 Fix signal width parametrization 2021-09-01 01:59:42 -07:00
Alex Forencich
fc835e0ab6 Use TX PTP CDC for both RX and TX due to synchronous clocking 2021-08-31 23:38:24 -07:00
Alex Forencich
82d0770daf Remove unused constraints file 2021-08-31 23:33:00 -07:00
Alex Forencich
c3d498101b Clarify widths 2021-08-31 23:32:42 -07:00
Alex Forencich
37a558e4f6 Add pipeline FIFOs 2021-08-31 22:30:45 -07:00
Alex Forencich
1fc991fc05 Convert fb2CG designs to use common core modules 2021-08-31 21:33:49 -07:00
Alex Forencich
915a915d6e Enable PCIe flow control in core tests 2021-08-31 20:38:08 -07:00
Alex Forencich
bd3fa6abfd Update vivado.mk 2021-08-31 20:03:33 -07:00
Alex Forencich
a5519cd607 Default to US+ configuration 2021-08-31 18:57:32 -07:00
Alex Forencich
bdbdc11841 Initial commit of core logic 2021-08-31 18:42:19 -07:00
Alex Forencich
9731ea5188 Add new PTP subsystem 2021-08-31 01:39:19 -07:00
Alex Forencich
cef2602efe Reorganize address space to place port registers in interface register space 2021-08-30 01:29:25 -07:00
Alex Forencich
d46cb16dbf Add scheduler block 2021-08-30 01:28:55 -07:00
Alex Forencich
d8615468e9 merged changes in eth 2021-08-30 01:28:13 -07:00
Alex Forencich
cee999a201 merged changes in axi 2021-08-30 01:28:08 -07:00
Alex Forencich
454d237ab2 Rename parameter 2021-08-30 01:27:53 -07:00
Alex Forencich
5f7b0292fc Print more PCIe information 2021-08-30 01:27:25 -07:00
Alex Forencich
a6a9a2ebd8 Update readme 2021-08-29 19:16:43 -07:00
Alex Forencich
5c2c6fd2bb Add AXI lite register interface modules 2021-08-29 19:09:52 -07:00
Alex Forencich
3db970636c merged changes in axis 2021-08-27 15:28:53 -07:00
Alex Forencich
6bcd96fa83 Bypass pipeline FIFO when length is zero 2021-08-27 13:54:14 -07:00
Alex Forencich
6b108481b8 Update interconnect address handling 2021-08-26 16:48:31 -07:00
Alex Forencich
e7de9b6ee6 Update PTP CDC instances 2021-08-26 01:07:56 -07:00
Alex Forencich
77938fa422 Update MAC modules for changes in FIFO modules 2021-08-26 00:55:12 -07:00
Alex Forencich
5273a8dda6 merged changes in axis 2021-08-26 00:14:22 -07:00
Alex Forencich
a613cc8a31 Fix alignment 2021-08-25 23:58:52 -07:00
Alex Forencich
6d70b0249e Update readme 2021-08-25 23:58:33 -07:00
Alex Forencich
6a030f5d5e Add axis_pipeline_fifo 2021-08-25 23:54:30 -07:00
Alex Forencich
92681fad8c Add DROP_OVERSIZE_FRAME parameter 2021-08-25 22:56:22 -07:00
Alex Forencich
0b2066abe3 Fix corner case with back-to-back single-cycle transfers 2021-08-25 19:19:30 -07:00