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2,139 Commits 1 Branch 0 Tags
Commit Graph

154 Commits

Author SHA1 Message Date
Alex Forencich
aa89471cca Add bus_num port to mqnic_core_pcie 2021-11-03 21:40:19 -07:00
Alex Forencich
7ac4797336 Add default_nettype none and resetall directives 2021-10-20 21:53:39 -07:00
Alex Forencich
607257d7bb Fix connections 2021-10-20 20:43:11 -07:00
Alex Forencich
2c038c9b7b Update FIFO instance 2021-10-13 16:44:05 -07:00
Alex Forencich
620791e562 Add TDMA testbench 2021-09-13 17:11:39 -07:00
Alex Forencich
ec89492d24 Fix control register addressing bug 2021-09-11 00:49:48 -07:00
Alex Forencich
d24c53a2ad Add application section 2021-09-09 16:01:26 -07:00
Alex Forencich
371717b854 Add block names 2021-09-09 14:12:41 -07:00
Alex Forencich
97e3daa36c Extract information from design instead of env vars 2021-09-08 16:44:58 -07:00
Alex Forencich
c920272e84 Use interface address widths directly instead of BAR size parameters 2021-09-08 14:51:18 -07:00
Alex Forencich
cef144e376 Expose DMA_LEN_WIDTH and DMA_TAG_WIDTH parameters 2021-09-08 00:18:11 -07:00
Alex Forencich
c00a53155d Fix alignment 2021-09-07 01:38:09 -07:00
Alex Forencich
bdd2312ecc More descriptive parameter and signal names for AXI lite control connections 2021-09-07 01:35:15 -07:00
Alex Forencich
8cf16c182b More descriptive parameter names (SYNC instead of INT) 2021-09-07 01:29:35 -07:00
Alex Forencich
15dec9458a Add statistics counter subsystem 2021-09-05 23:03:22 -07:00
Alex Forencich
9ccd43d470 Add statistics collection modules 2021-09-05 18:28:37 -07:00
Alex Forencich
5d760851ac Limit queue manager pipelines to a single AXI lite operation 2021-09-05 12:46:56 -07:00
Alex Forencich
ef00d5ccfd Add parameters for FIFO output pipeline register depth 2021-09-02 14:45:18 -07:00
Alex Forencich
f3eeb653d1 Fix test 2021-09-02 00:00:37 -07:00
Alex Forencich
de869347cd Register interrupt signal 2021-09-01 13:14:02 -07:00
Alex Forencich
df9523011c Normalize instance names 2021-09-01 02:14:53 -07:00
Alex Forencich
37a558e4f6 Add pipeline FIFOs 2021-08-31 22:30:45 -07:00
Alex Forencich
915a915d6e Enable PCIe flow control in core tests 2021-08-31 20:38:08 -07:00
Alex Forencich
a5519cd607 Default to US+ configuration 2021-08-31 18:57:32 -07:00
Alex Forencich
bdbdc11841 Initial commit of core logic 2021-08-31 18:42:19 -07:00
Alex Forencich
9731ea5188 Add new PTP subsystem 2021-08-31 01:39:19 -07:00
Alex Forencich
cef2602efe Reorganize address space to place port registers in interface register space 2021-08-30 01:29:25 -07:00
Alex Forencich
d46cb16dbf Add scheduler block 2021-08-30 01:28:55 -07:00
Alex Forencich
454d237ab2 Rename parameter 2021-08-30 01:27:53 -07:00
Alex Forencich
34150323df Remove obsolete packet table size parameters 2021-08-20 18:15:06 -07:00
Alex Forencich
a19474f9dd Use AXI lite crossbar 2021-08-11 01:31:34 -07:00
Alex Forencich
e0e34a9f0d Update designs for PCIe module changes 2021-08-02 23:04:52 -07:00
Alex Forencich
c926fd2ca1 Remove extraneous imports 2021-06-28 22:35:22 -07:00
minseongg
9af504a6c0 Update cmac_pad testbench 2021-06-28 22:33:57 -07:00
minseongg
8db2faddc6 Update cmac_pad testbench 2021-06-28 22:33:57 -07:00
minseongg
dc5c8232f9 Add cmac_pad testbench 2021-06-28 22:33:57 -07:00
Alex Forencich
0a7f1ccbbe Remove string parameters 2021-06-02 18:18:23 -07:00
Alex Forencich
15cb21dbd1 Reorganize timing constraints 2021-05-20 15:24:01 -07:00
Alex Forencich
32abea89fa Update testbenches 2021-03-06 20:30:25 -08:00
Alex Forencich
a3c104f7dd Connect write done signals 2021-02-24 15:07:26 -08:00
Alex Forencich
c0c2f933c0 Rework sim_build output directory, fix default makefile target 2020-12-29 17:28:53 -08:00
Alex Forencich
0c0fdc479b Update testbenches for async send/recv 2020-12-18 17:40:36 -08:00
Alex Forencich
b5ee772761 Migrate test infrastructure to cocotb 2020-12-15 16:52:20 -08:00
Alex Forencich
3003b3228d Fix backpressure bug in TX checksum module 2020-12-12 21:51:54 -08:00
Alex Forencich
91edbbf3dc Rename port and interface modules 2020-11-26 15:05:59 -08:00
Alex Forencich
0d1617c05c Update DMA RAM instances 2020-09-25 21:51:31 -07:00
Alex Forencich
a37d9b3465 New transceiver control reigster definitions 2020-09-19 17:25:58 -07:00
Alex Forencich
3284ec3848 New I2C register definitions 2020-09-19 17:25:58 -07:00
Alex Forencich
cbaffeeac7 Limit RX DMA size to configured MTU size 2020-08-25 18:48:17 -07:00
Alex Forencich
495178e1dc Fix mask 2020-07-28 18:30:52 -07:00