100 Commits

Author	SHA1	Message	Date
Alex Forencich	d16f19f67e	Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream rate limiter	2017-11-20 21:31:41 -08:00
Alex Forencich	772e433ee9	Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream frame length adjuster	2017-11-20 21:30:26 -08:00
Alex Forencich	de590517a9	Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream switch	2017-11-20 20:17:20 -08:00
Alex Forencich	91a7169f46	Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream crosspoint	2017-11-20 20:16:21 -08:00
Alex Forencich	496c63bd1c	Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream arbitrated mux	2017-11-20 20:15:08 -08:00
Alex Forencich	57e700f802	Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream demux	2017-11-20 20:14:20 -08:00
Alex Forencich	9e4aa38750	Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream mux	2017-11-20 20:13:53 -08:00
Alex Forencich	d50c767482	Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream adapter	2017-11-20 20:12:43 -08:00
Alex Forencich	fdb881719c	Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream async frame FIFO	2017-11-20 20:12:02 -08:00
Alex Forencich	1c7362c717	Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream frame FIFO	2017-11-20 20:11:44 -08:00
Alex Forencich	7d237f55c1	Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream async FIFO	2017-11-20 20:11:08 -08:00
Alex Forencich	190d75df9d	Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream FIFO	2017-11-20 20:10:41 -08:00
Alex Forencich	a5524287ca	Consolidate, add configuration parameters, and add tid and tdest ports to AXI stream register	2017-11-20 20:09:48 -08:00
Alex Forencich	aebe0549dd	Happy new year	2017-05-18 13:35:11 -07:00
Alex Forencich	0691c9d61b	Fix output pipeline issue	2016-09-02 10:43:21 -07:00
Alex Forencich	4245e2bf00	Rework mux logic	2016-08-24 16:53:13 -07:00
Alex Forencich	3207a2b7d2	Remove redundant code	2016-08-23 09:25:19 -07:00
Alex Forencich	24f7aee8b2	Add COBS encoder and decoder modules and testbench	2016-08-21 20:03:54 -07:00
Alex Forencich	a961a9756a	Add FIFO output pipeline registers to aid block RAM output timing closure	2016-08-04 18:03:00 -07:00
Alex Forencich	b44e401b95	Update async FIFO resets	2016-07-27 13:42:44 -07:00
Alex Forencich	06bfa1944c	Add AXI stream switch module, generator script, and testbench	2016-07-25 13:12:10 -07:00
Alex Forencich	d023213fda	Support generating asymmetric crosspoints	2016-07-24 13:06:59 -07:00
Alex Forencich	52fc34d82e	Assume first tkeep bit is always set	2016-07-20 12:36:59 -07:00
Alex Forencich	6fe4a033e5	Add dedicated pipeline registers for RAM addresses that are not reset	2016-06-27 12:25:18 -07:00
Alex Forencich	385c9cc90a	Fix Vivado block RAM inference	2016-06-27 12:10:36 -07:00
Alex Forencich	4f66059d21	Adjust constant naming	2016-06-27 11:27:04 -07:00
Alex Forencich	f89620008d	Remove reset dependence	2016-06-27 11:26:15 -07:00
Alex Forencich	cab7d367f2	Fix default width	2016-06-27 11:24:36 -07:00
Alex Forencich	be4034071b	Happy new year	2016-01-05 00:24:20 -08:00
Alex Forencich	7a9fdb5fc3	Add default case statements to avoid inferring latches	2015-11-09 14:54:14 -08:00
Alex Forencich	0d22a35bd8	Update output registers, remove extraneous resets, fix constant widths	2015-11-08 23:05:38 -08:00
Alex Forencich	0a79f24d3c	Do not reset datapath registers in crosspoint switch	2015-11-08 17:27:13 -08:00
Alex Forencich	5fb4cb159b	Reorganize register modules	2015-11-08 16:18:29 -08:00
Alex Forencich	0f0ebfb87d	Reorganize FIFO modules	2015-11-07 01:15:11 -08:00
Alex Forencich	7ea566e6d2	Update generate scripts to use argparse	2015-10-19 19:15:38 -07:00
Alex Forencich	dcad442e7c	Improve timing performance of frame length adjust module	2015-10-19 00:30:50 -07:00
Alex Forencich	364b537312	Synchronize status signals for both clock domains in async frame FIFO	2015-10-09 15:14:54 -07:00
Alex Forencich	382226ad59	Don't accept data until reset is complete	2015-10-08 23:46:59 -07:00
Alex Forencich	90ac361df5	Internal synchronous reset on async FIFOs	2015-10-08 13:03:42 -07:00
Alex Forencich	30a35c3d73	Convert async fifo to common reset	2015-10-08 12:52:51 -07:00
Alex Forencich	ca11618e6d	Convert to synchronous resets	2015-10-08 11:26:32 -07:00
Alex Forencich	26b165227c	Update for compatibility with older versions of Python	2015-07-14 08:27:49 -07:00
Alex Forencich	ac97cffc2b	Properly reset all registers	2015-07-13 23:15:09 -07:00
Alex Forencich	dfab866e99	Remove unused reg	2015-07-13 23:09:02 -07:00
Alex Forencich	04e4ccc517	Update for compatibility with older version of Python	2015-07-09 11:25:49 -07:00
Alex Forencich	f387e4c300	Remove unused register	2015-07-09 11:13:12 -07:00
Alex Forencich	6bd7309b9d	Properly reset all registers	2015-07-09 11:11:32 -07:00
Alex Forencich	87fe1a561f	Add AXI stream tap modules	2015-06-22 14:56:56 -07:00
Alex Forencich	c15761068a	Add AXI stream frame length adjust modules	2015-06-05 17:04:10 -07:00
Alex Forencich	3d17cc1cee	Adjust rate limiter framing logic	2015-05-12 17:58:09 -07:00