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Commit Graph

25 Commits

Author SHA1 Message Date
Alex Forencich
d24c53a2ad Add application section 2021-09-09 16:01:26 -07:00
Alex Forencich
0c0fdc479b Update testbenches for async send/recv 2020-12-18 17:40:36 -08:00
Alex Forencich
b5ee772761 Migrate test infrastructure to cocotb 2020-12-15 16:52:20 -08:00
Alex Forencich
a37d9b3465 New transceiver control reigster definitions 2020-09-19 17:25:58 -07:00
Alex Forencich
3284ec3848 New I2C register definitions 2020-09-19 17:25:58 -07:00
Alex Forencich
495178e1dc Fix mask 2020-07-28 18:30:52 -07:00
Alex Forencich
4e958096b2 Update driver model to set MTU registers 2020-05-01 19:19:56 -07:00
Alex Forencich
8b535e54ac Add MTU registers 2020-05-01 18:55:01 -07:00
Alex Forencich
1f76606667 Move TDMA registers 2020-05-01 16:55:57 -07:00
Alex Forencich
9e64d19ea5 Use scatter descriptor blocks in driver model 2020-04-21 01:04:07 -07:00
Alex Forencich
2c6e9673f7 Add log_desc_block_size ring parameter in driver model 2020-04-21 00:58:12 -07:00
Alex Forencich
a196cd227c Enable bus mastering and MSI in driver model 2020-03-12 15:32:08 -07:00
Alex Forencich
457f4d7f3f Use configured ring stride 2020-03-12 15:28:00 -07:00
Alex Forencich
0c32192226 Use constants instead of magic numbers 2020-03-12 15:08:20 -07:00
Alex Forencich
1216f7a76e Offset packet start by 10 bytes to match Linux kernel skb alignment 2020-03-08 21:56:08 -07:00
Alex Forencich
4dd5104f4d Stripe completion queues across event queues 2020-03-06 00:58:30 -08:00
Alex Forencich
f97ff4407b Change driver model max packet size 2019-12-23 14:41:52 -08:00
Alex Forencich
463f2053b0 Add port register port_mtu 2019-11-18 16:30:32 -08:00
Alex Forencich
489506e4c0 Add FPGA ID register 2019-11-17 12:46:27 -08:00
Alex Forencich
f53a6b20e8 Add timeslot count to port registers 2019-11-05 16:59:40 -08:00
Alex Forencich
e92485a41e Fix register definitions 2019-11-05 16:44:57 -08:00
Alex Forencich
a4132cfda7 Integrate TX checksum offload 2019-08-22 00:45:09 -07:00
Alex Forencich
7b2a0d5032 Sync driver model 2019-08-20 01:36:22 -07:00
Alex Forencich
d99f40db08 Add port CSRs 2019-08-13 00:27:09 -07:00
Alex Forencich
fcd8b1b8e9 Add driver simulation model 2019-07-17 16:46:12 -07:00