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mirror of https://github.com/corundum/corundum.git synced 2025-01-30 08:32:52 +08:00

14 Commits

Author SHA1 Message Date
Alex Forencich
d3942da875 fpga: Add clock info register block
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-10-15 19:45:02 -07:00
Alex Forencich
d0cc106783 fpga: Remove redundant RX_RSS_ENABLE parameter
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-10-13 17:10:25 -07:00
Alex Forencich
01df80df86 fpga/mqnic: Disable MIGs by default
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-10-12 23:57:27 -07:00
Alex Forencich
5e52a52f5e fpga/mqnic: Add MIGs and HBM controllers for most boards
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-10-12 19:00:49 -07:00
Alex Forencich
eb990643f2 fpga/mqnic: various minor cleanup
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-10-12 17:12:07 -07:00
Alex Forencich
5f1e74b0e1 Add PROJECT variable, remove multiple stem matches
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-10-11 13:33:09 -07:00
Alex Forencich
7017e7d49b Explicitly set top module
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-10-11 12:29:01 -07:00
Alex Forencich
ceb6a9ca06 Update clean target
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-10-11 12:26:39 -07:00
Alex Forencich
9c98f12392 Write debug probes file alongside bit file
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-10-10 23:37:54 -07:00
Alex Forencich
9628401780 Normalize output file location
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-10-10 21:47:53 -07:00
Alex Forencich
d7904b8007 fpga: Add support for IRQ rate limiting
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-09-04 15:24:40 -07:00
Alex Forencich
1486da601f fpga: Add clock period parameters
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-09-04 12:03:35 -07:00
Alex Forencich
647a168299 Enable more peripherals in Zynq designs
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-08-16 18:49:02 -07:00
Alex Forencich
1b9f5d1032 fpga/mqnic/ZCU102: Add 10G mqnic design for ZCU102
Signed-off-by: Alex Forencich <alex@alexforencich.com>
2022-08-16 01:44:52 -07:00