Alex Forencich
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d9e4b82f7a
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fpga: PTP sample clock is no longer optional, so remove PTP_USE_SAMPLE_CLOCK parameter
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-09-24 13:52:06 -07:00 |
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Alex Forencich
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5e53dd10ea
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fpga/mqnic: Increase RX FIFO size
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-09-11 22:47:35 -07:00 |
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Alex Forencich
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9963674c61
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Add flow control
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-09-09 19:01:36 -07:00 |
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Alex Forencich
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e0b31d9b94
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fpga/mqnic: Add MAC-related parameters
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-09-07 18:35:42 -07:00 |
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Alex Forencich
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31ced63c91
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fpga/mqnic: Add missing XGMII parameter connections
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-09-07 18:30:13 -07:00 |
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Alex Forencich
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2e387d3630
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fpga/mqnic: Ensure class code lookup assistant is disabled in PCIe core instances
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-09-05 23:44:12 -07:00 |
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Alex Forencich
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06226ac777
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fpga/mqnic: Fix PCIe subsystem vendor IDs on UltraScale devices
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-09-04 23:05:25 -07:00 |
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Alex Forencich
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36576d8981
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Update MAC and PHY instances
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-08-28 17:22:34 -07:00 |
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Alex Forencich
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c5af0f726a
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fpga/mqnic: Use arrays for QSFP pins
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-08-28 12:21:09 -07:00 |
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Alex Forencich
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f1884b98bf
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Add unified 10G/25G mqnic design for BittWare XUSP3S board
Signed-off-by: Alex Forencich <alex@alexforencich.com>
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2023-08-22 12:55:11 -07:00 |
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