17 Commits

Author	SHA1	Message	Date
Alex Forencich	0ca8c9a59b	Update example design timing constraints	2019-03-28 17:59:30 -07:00
Alex Forencich	cd6b87e984	Enable bitstream compression in example designs	2019-02-06 21:25:30 -08:00
Alex Forencich	0a6bee6d69	Update example designs	2018-11-08 09:17:29 -08:00
Alex Forencich	7d6889add6	Update example designs	2018-10-30 21:32:32 -07:00
Alex Forencich	e4672915e6	Update testbenches to use instances()	2018-06-13 22:43:11 -07:00
Alex Forencich	298ae4defa	Update MAC module instantiation	2018-06-13 22:16:02 -07:00
Alex Forencich	0fd157964a	Happy new year	2018-02-26 12:50:51 -08:00
Alex Forencich	bd27156f35	AXI stream updates	2018-02-26 00:08:08 -08:00
Alex Forencich	9fdc36450a	Update NexysVideo reference design	2017-05-31 19:44:39 -07:00
Alex Forencich	0fc986041e	Fix example design LED logic	2017-05-19 17:44:29 -07:00
Alex Forencich	9b2ac9dfc1	Happy new year	2017-05-18 13:47:45 -07:00
Alex Forencich	3b47b422fa	Fix Vivado clock groups	2016-10-06 17:52:23 -07:00
Alex Forencich	270641b7a3	Update UDP modules and example designs to utilize UDP checksum modules	2016-09-30 22:15:21 -07:00
Alex Forencich	15330486e8	Convert GMII and RGMII shims to use generic IO components	2016-09-29 20:10:10 -07:00
Alex Forencich	88150c9d5f	Update and rework endpoints, update testbenches	2016-09-13 15:24:02 -07:00
Alex Forencich	1f52bf826d	Update vivado.mk	2016-07-05 11:17:16 -04:00
Alex Forencich	cbf1df718a	Add example design for Digilent Nexys Video board	2016-06-29 12:00:05 -07:00