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309 Commits

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Author SHA1 Message Date
Alex Forencich
dad637bd00 Properly handle zero-length DMA operations 2021-07-25 01:36:40 -07:00
Alex Forencich
59c026b1b8 Fix parameters 2021-07-24 02:02:30 -07:00
Alex Forencich
3e03b20bc7 Properly handle zero-length PCIe read and write operations 2021-07-24 01:13:25 -07:00
Alex Forencich
c7a59c5f15 Split read requests on RCB 2021-06-27 01:31:40 -07:00
Alex Forencich
36a361d7c3 Update test durations 2021-06-18 18:42:44 -07:00
Alex Forencich
6b0076debc Work around pytest-split bug 2021-06-18 18:41:26 -07:00
Alex Forencich
ccc44d7dbb Use 64 bit BARs in example designs 2021-06-16 23:23:53 -07:00
Alex Forencich
a79027fdd1 Remove DEV_BAR_CNT define 2021-06-16 21:36:34 -07:00
Alex Forencich
31378c4e85 Remove string parameters 2021-06-02 17:05:29 -07:00
Alex Forencich
e4e05ed1e3 Update readme 2021-06-01 16:29:52 -07:00
Alex Forencich
0d21ea80ea Update readme 2021-05-18 22:16:50 -07:00
Alex Forencich
1a046d8e82 Update testbenches 2021-04-15 23:30:14 -07:00
Alex Forencich
77ff92f02b Avoid sampling own outputs 2021-04-05 20:38:05 -07:00
Alex Forencich
5f90e39e59 Use correct assignment type 2021-03-30 21:53:01 -07:00
Alex Forencich
4adee5db8f Use release version of cocotb for CI 2021-03-17 22:54:46 -07:00
Alex Forencich
04cbbeb879 Add bus objects for DMA RAM 2021-03-17 22:12:42 -07:00
Alex Forencich
bdfeaa84ca Update testbenches 2021-03-06 20:06:23 -08:00
Alex Forencich
78d755ea9a Minor optimization 2021-02-28 22:31:29 -08:00
Alex Forencich
0c6bb169bc Rework FIFO distributed RAM init code 2021-02-28 22:18:54 -08:00
Alex Forencich
670dfa0d11 Fix pcie_us_axi_dma_wr testbench file list 2021-02-28 19:50:45 -08:00
Alex Forencich
5715e12d41 Remove tag manager module 2021-02-28 19:37:16 -08:00
Alex Forencich
266fed8d20 Update example design file list 2021-02-28 19:35:35 -08:00
Alex Forencich
438a4fdcc9 Use FIFOs for PCIe tag management in PCIe read DMA modules 2021-02-28 19:34:24 -08:00
Alex Forencich
a3f805a0c3 Add pipeline register 2021-02-28 11:34:29 -08:00
Alex Forencich
92951723aa Offset stored address by TLP byte length to eliminate updating stored address 2021-02-28 01:36:03 -08:00
Alex Forencich
603784b742 Fix operation init handling 2021-02-26 01:19:56 -08:00
Alex Forencich
912ef845a3 Rename tag to pcie_tag 2021-02-25 23:54:40 -08:00
Alex Forencich
062495b780 Remove redundant parameter PCIE_EXT_TAG_ENABLE 2021-02-25 18:20:08 -08:00
Alex Forencich
8294eecd65 Remove redundant parameter PCIE_TAG_WIDTH 2021-02-25 18:10:59 -08:00
Alex Forencich
8cfbe18335 Use FIFO for op tag management in PCIe read DMA modules 2021-02-25 16:30:23 -08:00
Alex Forencich
41d0e7cb7e Minor optimization 2021-02-24 14:48:14 -08:00
Alex Forencich
63006e8092 Add output FIFO to DMA IF mux for read response data 2021-02-24 13:54:40 -08:00
Alex Forencich
ed29997a59 Add write done tracking to DMA IF mux 2021-02-24 13:51:50 -08:00
Alex Forencich
6fb2eb6b4e Remove unnecessary delays from testbenches 2021-02-24 13:50:45 -08:00
Alex Forencich
40a191a06d Add output FIFO and write done tracking to ultrascale PCIe read DMA interface 2021-02-24 13:50:05 -08:00
Alex Forencich
9c8417799d Add output FIFO and write done tracking to AXI stream sink DMA client 2021-02-24 13:48:56 -08:00
Alex Forencich
070689692d Add wr_done signal to RAM model and placeholders to DMA components 2021-02-24 13:47:53 -08:00
Alex Forencich
057a93e07a Sync data handling 2021-02-16 13:56:44 -08:00
Alex Forencich
742ef1c272 Add same-width test cases to DMA clients 2021-02-16 01:26:05 -08:00
Alex Forencich
33bc8c21ae Fix bug in DMA client source when AXI stream width matches RAM interface width 2021-02-16 01:25:07 -08:00
Alex Forencich
20b2414d7a Use reg instead of next for read operation generation 2021-02-15 00:09:03 -08:00
Alex Forencich
93e2769269 Make 64-bit-only states no-ops for other interface widths 2021-02-14 15:17:28 -08:00
Alex Forencich
a78674c06a Refactor TLP header and tuser computation 2021-02-14 11:16:25 -08:00
Alex Forencich
93496729f3 Update testbench 2021-02-12 16:59:13 -08:00
Alex Forencich
fb1d64e710 Add pipeline stage to dma_if_pcie_us_wr 2021-02-12 16:58:35 -08:00
Alex Forencich
6d98a7c0e6 Ensure output FIFOs use distributed RAM 2021-02-11 00:14:36 -08:00
Alex Forencich
5f7697178b Remove await ReadOnly 2021-02-10 18:42:32 -08:00
Alex Forencich
ba1b0ef20b Add output FIFO to write DMA interface module 2021-02-10 17:29:17 -08:00
Alex Forencich
f76ed26503 Add output FIFO to AXI stream source DMA client 2021-02-10 17:28:08 -08:00
Alex Forencich
c6d8983fcd Add wr_done output to DMA RAMs 2021-02-07 23:47:46 -08:00