11 Commits

Author	SHA1	Message	Date
Alex Forencich	3e03b20bc7	Properly handle zero-length PCIe read and write operations	2021-07-24 01:13:25 -07:00
Alex Forencich	af09059248	Update AXI lite master module to support 512 bit interface	2019-10-14 15:58:38 -07:00
Alex Forencich	a92722173a	Handle ultrascale plus interface widths	2019-10-04 16:29:11 -07:00
Alex Forencich	e97e4ad423	Parametrize tuser signal widths	2019-09-26 23:30:03 -07:00
Alex Forencich	f518aec219	Include instance names in error messages	2019-07-25 16:38:54 -07:00
Alex Forencich	c75f29c648	Add parameter documentation	2019-07-24 18:01:13 -07:00
Alex Forencich	8c7eb13c0d	Properly handle truncated packet	2018-11-26 13:12:50 -08:00
Alex Forencich	a6809a6b57	Use constants instead of magic numbers	2018-11-26 13:07:50 -08:00
Alex Forencich	c3d4aeda48	Use logical operators	2018-11-08 23:36:05 -08:00
Alex Forencich	b5cfb9d025	Handshaking fixes	2018-09-26 20:11:25 -07:00
Alex Forencich	c25a13041e	Add Ultascale PCIe AXI lite master module and testbenches	2018-09-25 21:09:20 -07:00