7 Commits

Author	SHA1	Message	Date
Alex Forencich	134ce04777	Add configurable serdes pipeline register chain	2019-06-19 00:57:28 -07:00
Alex Forencich	82fe5a6bdd	Add PTP timestamp capture logic to MACs	2019-06-07 16:38:36 -07:00
Alex Forencich	659aa67481	Pack start packet strobes into the same signal	2019-06-06 17:13:14 -07:00
Alex Forencich	79ec137243	Add PRBS31 generation and checking to 10G PHY	2019-05-10 20:28:45 -07:00
Alex Forencich	b7d297850c	Move 10G PHY interface logic into separate modules	2019-05-10 14:56:18 -07:00
Alex Forencich	696c634726	Add rx_bad_block outputs	2019-04-17 00:16:45 -07:00
Alex Forencich	ec38440d89	Add 10G Ethernet MAC/PHY combination modules and testbenches	2019-01-31 18:13:07 -08:00