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Author SHA1 Message Date
Andreas Braun
dc77c9e92a ZCU106/fpga_zynqmp: Reduce number of IRQs to number of CPU cores 
Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
Signed-off-by: Andreas Braun <andreas.braun@missinglinkelectronics.com>
 2022-03-31 17:22:27 +02:00
Andreas Braun
dce11522fa ZCU106/fpga_zynqmp: Reduce number of RX/TX queues to 32 
Signed-off-by: Joachim Foerster <joachim.foerster@missinglinkelectronics.com>
 2022-03-31 17:22:27 +02:00
Andreas Braun
35517037e6 ZCU106/: Add design based on ZynqMP PS as host system, Vivado v2021.1 
Signed-off-by: Andreas Braun <andreas.braun@missinglinkelectronics.com>
Signed-off-by: Joachim Förster <joachim.foerster@missinglinkelectronics.com>
 2022-03-31 17:22:27 +02:00
Alex Forencich
b7aa4f77d7 merged changes in eth 2022-03-30 16:32:56 -07:00
Alex Forencich
84004c720d merged changes in axis 2022-03-30 16:03:34 -07:00
Alex Forencich
073d50d9dc Round up default KEEP_WIDTH settings when DATA_WIDTH is not a multiple of 8 2022-03-30 16:02:17 -07:00
Alex Forencich
f082196b4a Expose EVENT_QUEUE_INDEX_WIDTH parameter at top-level 2022-03-29 23:15:06 -07:00
Alex Forencich
4310c3e0e7 Pass SCHED_PER_IF and PTP_PORT_CDC_PIPELINE parameters through to application block 2022-03-28 21:57:53 -07:00
Alex Forencich
a98443a95b Update parameter documentation 2022-03-28 21:55:04 -07:00
Alex Forencich
3b8643877d Support bare device name 2022-03-28 18:06:22 -07:00
Alex Forencich
cbd9d0dfc6 Expose port and scheduler block counts in IF control block; update driver model, driver, and userspace tools to handle scheduler blocks separately from ports 2022-03-28 17:23:27 -07:00
Alex Forencich
09128df360 Add SCHED_PER_IF parameter to split scheduler count from port count 2022-03-28 15:20:33 -07:00
Alex Forencich
dfae34ed25 Pass through PTP pipelining settings 2022-03-28 00:50:29 -07:00
Alex Forencich
ad8ffef2a0 merged changes in eth 2022-03-27 23:49:57 -07:00
Alex Forencich
6f2d581d62 Add output pipeline to PTP clock CDC module 2022-03-27 23:47:14 -07:00
Alex Forencich
945f22fd33 Add output pipeline to PTP clock module 2022-03-27 23:46:49 -07:00
Alex Forencich
6daf1171b5 Improve ioctl implementation to support arbitrary number of regions 2022-03-26 00:24:02 -07:00
Alex Forencich
2babcdd16e Fix indentation 2022-03-26 00:18:07 -07:00
Alex Forencich
e95c132045 Route PCIe user reset through BUFG 2022-03-25 01:26:29 -07:00
Alex Forencich
6f197c7cb4 Add PHY instances to Ethernet pblocks 2022-03-24 21:30:55 -07:00
Ulrich Langenbach
984a58684c fix partial initialisation of memory 
the fixed issue has been introduced in 0560f98e799d741d62522e61bf23321fc3f2880b
 2022-03-24 15:50:25 -07:00
Alex Forencich
fca0b080a0 Improve performance tuning section relating to NUMA 2022-03-24 00:51:43 -07:00
Alex Forencich
8fbe46aa31 Update ethtool API implementation 2022-03-22 23:48:13 -07:00
Alex Forencich
c118565d21 Fix EEPROM-related error handling in ethtool interface code 2022-03-20 23:07:45 -07:00
Alex Forencich
8aa2185bfb Fix MCS file addresses for main bitstream 2022-03-20 22:52:14 -07:00
Alex Forencich
b83270c953 Fix rev file numbering for fallback bitstream generation 2022-03-20 22:50:37 -07:00
Alex Forencich
d2f5a89b5f Update build images script for ubuntu 2022-03-17 17:46:06 -07:00
Alex Forencich
056f78716a Add pipeline registers 2022-03-17 15:39:44 -07:00
Alex Forencich
0e15a7a16b Avoid critical warning from placement constraints when configured with a single interface 2022-03-17 15:39:13 -07:00
Alex Forencich
6cb5297e28 Fix TDMA BER pipeline register 2022-03-17 13:28:41 -07:00
Alex Forencich
869e7e70d4 Add Ethernet interface placement constraints for AU250 2022-03-17 00:51:14 -07:00
Alex Forencich
059d9b5e37 Add Ethernet interface placement constraints for AU200 2022-03-17 00:51:05 -07:00
Alex Forencich
28558449f6 Add Ethernet interface placement constraints for VCU1525 2022-03-17 00:48:52 -07:00
Alex Forencich
0928f56a45 Add Ethernet interface placement constraints for VCU118 2022-03-17 00:48:44 -07:00
Alex Forencich
cb44b2ee60 merged changes in eth 2022-03-16 21:09:16 -07:00
Alex Forencich
a61ac12962 Add Ethernet interface placement constraints for ADM-PCIE-9V3 2022-03-16 21:08:01 -07:00
Alex Forencich
e317439843 Add Ethernet interface placement constraints for fb2CG@KU15P 2022-03-16 21:07:53 -07:00
Alex Forencich
108c02d721 Simplify logic in PTP clock CDC module 2022-03-16 19:01:17 -07:00
Alex Forencich
0f2db26a8e Simplify logic in PTP clock module 2022-03-16 19:01:00 -07:00
Alex Forencich
23fb9d0bd8 Remove deprecated assignments 2022-03-16 18:43:36 -07:00
Alex Forencich
744a1126e0 Update cocotbext-pcie 2022-03-15 21:51:56 -07:00
Alex Forencich
e983ad519f Update documentation URL 2022-03-15 17:56:38 -07:00
Alex Forencich
0a385385d4 Update list of designs 2022-03-15 17:56:02 -07:00
Alex Forencich
623b758598 Print PCIe bridge information during driver load 2022-03-15 17:55:29 -07:00
Alex Forencich
fdabde6d0f Remove deprecated assignments 2022-03-15 17:52:12 -07:00
Alex Forencich
1291d7b1b7 Add pipeline registers to TDMA BER modules 2022-03-15 17:40:27 -07:00
Alex Forencich
25421b8994 Update placement constraints 2022-03-15 15:28:43 -07:00
Alex Forencich
39691759aa Unified 10G/25G design for VCU118 2022-03-14 21:40:29 -07:00
Alex Forencich
202f407686 Unified 10G/25G design for VCU1525 2022-03-14 21:39:55 -07:00
Alex Forencich
b10ff8b4a7 Unified 10G/25G design for AU250 2022-03-14 21:39:13 -07:00