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334 Commits

Author SHA1 Message Date
Alex Forencich
dce0c92a57 Rework PHC to register shared adder outputs for improved timing performance 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-12-02 00:53:02 -08:00
Alex Forencich
dd97924714 Prevent stale data frim being used to sync leaf clock 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-12-01 22:05:53 -08:00
Alex Forencich
f0c47db509 Improve tolerance of sample point synchronization 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-12-01 22:03:14 -08:00
Alex Forencich
a2294c56a5 Rewrite gain scheduling 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-12-01 22:02:40 -08:00
Alex Forencich
36cf9c9b06 Remove unnecessary shadow valid registers 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-12-01 14:03:55 -08:00
Alex Forencich
5560fa2b32 Fix timestamp capture/sync logic 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-30 14:05:16 -08:00
Alex Forencich
bd8e8e5b20 Add PTP time distribution components 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-07 13:07:15 -08:00
Alex Forencich
01badce3a1 Remove unnecessary resets 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-11-01 18:30:32 -07:00
Alex Forencich
5ff1e17a29 Add missing assign to frame_min_count_reg in axis_baser_tx_64 module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-24 13:35:29 -07:00
Alex Forencich
90e6dfc638 Use phase detector in PTP CDC module for coarse period tuning, use 9 LSBs of timestamp for fine sync to avoid rollover corrections, reduce FNS comparison width to 4 bits 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-23 14:58:44 -07:00
Alex Forencich
f9ae6da8bd Improve PTP CDC module testbench 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-23 14:33:14 -07:00
Alex Forencich
5a37442706 Merge FNS registers into NS registers in PTP CDC module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-22 22:52:59 -07:00
Alex Forencich
b0a4d75fd9 Remove extraneous code 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-22 01:08:01 -07:00
Alex Forencich
4a32c86f07 Match integrator width to period register width in PTP CDC module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-22 01:07:43 -07:00
Alex Forencich
cf441f004d Rename source sync signals in PTP CDC module for consistency 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-22 01:07:12 -07:00
Alex Forencich
4b1f48ab5b Parameter clean-up in PTP CDC module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-21 16:34:05 -07:00
Alex Forencich
aad30d09a1 Make FNS_WIDTH an internal parameter in PTP CDC module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-21 16:30:29 -07:00
Alex Forencich
98b4fbb56d Remove USE_SAMPLE_CLOCK parameter in PTP CDC module 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-09-18 16:58:02 -07:00
Alex Forencich
fa05d4ff3c Add TX and RX enable inputs to MACs 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-24 01:24:33 -07:00
Alex Forencich
20c542051d Use cfg prefix for configuration signals 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-08-22 17:14:52 -07:00
Alex Forencich
70cc19ff15 Add MAC control layer to core 1G and 10G MAC modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-23 22:24:42 -07:00
Alex Forencich
ba5a883433 Add pause/PFC modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-23 16:31:33 -07:00
Alex Forencich
6d5cda5986 Add MAC control layer modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-22 00:47:15 -07:00
Alex Forencich
2858aaaef7 Add TX PTP timestamp enable bit in tuser 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-17 10:58:40 -07:00
Alex Forencich
9665df8a44 Fix PTP timestamping in 1G MAC 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-08 01:41:14 -07:00
Alex Forencich
1f0b6a625c PTP parameter clean-up 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-06 16:46:32 -07:00
Alex Forencich
9dafc3aaee Use internal BYTE_LANES parameter 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-07-06 16:28:08 -07:00
Alex Forencich
f705646e3e Pull out header size as a parameter 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-06-29 15:48:39 -07:00
Alex Forencich
77adf30dad Add missing serdes_rx_reset_req output to 10G MAC+PHY modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-02-22 17:36:01 -08:00
Alex Forencich
450765187e Update lfsr.v 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-15 12:36:03 -08:00
Alex Forencich
cb1dc8fb15 Optimize FCS verification in 10G/25G MAC modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-13 15:47:30 -08:00
Alex Forencich
713b138ece Fix timing of IDDR2 on Spartan 6 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2023-01-01 21:44:15 -08:00
Alex Forencich
a1abc97e2a ISE does not support clog2 in localparam 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-12-27 18:26:47 -08:00
Alex Forencich
2199a15c75 Force possible floating point parameter value to integer when taking clog2 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-01 23:56:27 -07:00
Alex Forencich
5e528e0057 Update FIFO PIPELINE_OUTPUT to RAM_PIPELINE 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-11-01 23:56:11 -07:00
Alex Forencich
e542d39a75 Fix assignment type 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-10-20 09:21:34 -07:00
Alex Forencich
40acee1bc5 Rework MAC PTP timestamp adjustment logic 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-25 16:35:26 -07:00
Alex Forencich
07aeae5c2f Rework lane swapping logic 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-25 15:06:09 -07:00
Alex Forencich
fbaa714d2a Remove unnecessary CRC resets 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-25 15:03:03 -07:00
Alex Forencich
cb273970c3 Rework MAC frame padding logic 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-24 22:46:03 -07:00
Alex Forencich
2ce89aec09 Use generate blocks for Ethernet FCS computation 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-24 19:52:55 -07:00
Alex Forencich
5f39d6ece6 Improve internal encoding to simplify logic 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-24 17:32:43 -07:00
Alex Forencich
c7f3b4632b Simplify logic 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-24 16:08:34 -07:00
Alex Forencich
2601127679 Remove unnecessary zeroing 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-24 14:09:09 -07:00
Alex Forencich
ebd5f04e2d Remove unnecessary resets 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-24 10:14:54 -07:00
Alex Forencich
c1e947dc3d Timing optimization of PTP modules 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-22 22:57:44 -07:00
Alex Forencich
db881ed551 Remove magic numbers 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-22 18:39:21 -07:00
Alex Forencich
4a16c9070b Fix mixed assignments 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-07-22 01:24:22 -07:00
Alex Forencich
85e4f1d8ba Add PHY RX status output for a more reliable link up indication 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 23:22:30 -07:00
Alex Forencich
a855fb3fb6 Use correct sync types 
Signed-off-by: Alex Forencich <alex@alexforencich.com>
 2022-05-16 23:22:01 -07:00