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Author SHA1 Message Date
Alex Forencich
e4b4762474 Handle some zero-valued signal width settings 2021-11-29 00:33:38 -08:00
Alex Forencich
907081d255 Add support to demux for routing by tdest 2021-11-28 23:09:10 -08:00
Alex Forencich
ccbca0c502 Add UPDATE_TID parameter to set MSBs of tid based on source port 2021-11-28 16:25:35 -08:00
Alex Forencich
24863398c5 Decouple tid/tdest signal widths for routing components 2021-11-25 01:18:51 -08:00
Alex Forencich
150d5ad04e Handle out-of-range select as drop 2021-11-24 14:58:16 -08:00
Alex Forencich
f40e68350c Remove deprecated assigments 2021-11-15 14:39:47 -08:00
Alex Forencich
8bd6c8ea34 Remove some lint 2021-11-07 18:23:13 -08:00
Alex Forencich
32d99b4dd9 Use constants from cocotbext-eth 2021-11-07 18:21:06 -08:00
Alex Forencich
4cda6b07dd Update readme 2021-11-03 00:48:59 -07:00
Alex Forencich
d052264659 Add 520N-MX 10G example design 2021-11-03 00:48:06 -07:00
Alex Forencich
9e44987f60 Reorganize PHY instances 2021-11-02 23:30:48 -07:00
Alex Forencich
728e86c554 Update QSF/SDC files 2021-11-02 23:30:06 -07:00
Alex Forencich
74f32c6a59 Add missing PHY instance ports 2021-11-02 20:28:26 -07:00
Alex Forencich
0aee872452 merged changes in axis 2021-11-02 20:23:33 -07:00
Alex Forencich
96a26e7a54 Add attributes to RAMs for proper synthesis in Quartus 2021-11-02 20:22:47 -07:00
Alex Forencich
6b18e56cb1 Add default_nettype none and resetall directives 2021-10-20 17:29:12 -07:00
Alex Forencich
9ff4454db0 Update makefiles 2021-10-20 17:21:58 -07:00
Alex Forencich
0f2478d68c Fix wires 2021-10-20 17:21:16 -07:00
Alex Forencich
1e6d667ae0 merged changes in axis 2021-10-20 15:36:38 -07:00
Alex Forencich
2972a1fa81 Add default_nettype none and resetall directives 2021-10-20 15:33:38 -07:00
Alex Forencich
786eabac4b Add missing wires 2021-10-20 02:01:33 -07:00
Alex Forencich
9f6f388a3c Rework GT instances in HTG9200 design 2021-10-20 00:57:11 -07:00
Alex Forencich
527c2f1b89 Rework GT instances in fb2CG@KU15P design 2021-10-20 00:56:13 -07:00
Alex Forencich
05770c5a1b Rework GT instances in VCU118 designs 2021-10-19 22:13:02 -07:00
Alex Forencich
531f751e67 Update VCU118 XDC 2021-10-19 22:11:56 -07:00
Alex Forencich
cf016dc4ee Rework GT instances in VCU108 design 2021-10-19 22:11:34 -07:00
Alex Forencich
1f76eb4534 Update VCU108 XDC 2021-10-19 22:10:32 -07:00
Alex Forencich
a1da0ba184 Rework GT instances in VCU1525 design 2021-10-19 18:40:32 -07:00
Alex Forencich
0b41dc4011 Rework GT instances in ZCU102 design 2021-10-19 18:38:22 -07:00
Alex Forencich
e3f8879474 Rework GT instances in ZCU106 design 2021-10-19 18:30:35 -07:00
Alex Forencich
4ce218bc5d Rework GT instances in ADM-PCIE-9V3 designs 2021-10-19 18:29:18 -07:00
Alex Forencich
21da6f58dc Rework GT instances in Alveo U280 design 2021-10-19 18:28:10 -07:00
Alex Forencich
4fdc6408bc Rework GT instances in Alveo U50 design 2021-10-19 18:14:50 -07:00
Alex Forencich
cc4256666a Rework GT instances in Alveo U250 design 2021-10-19 17:47:15 -07:00
Alex Forencich
f11f7ecac9 Rework GT instances in Alveo U200 design 2021-10-19 17:45:43 -07:00
Alex Forencich
38e3244caa Rework GT instances in ExaNIC X10 design 2021-10-18 00:34:06 -07:00
Alex Forencich
fa77fe54f3 Rework GT instances in ExaNIC X25 design 2021-10-18 00:32:37 -07:00
Alex Forencich
4aa672f8f3 Update example designs 2021-10-17 20:20:26 -07:00
Alex Forencich
625c48c59c Add transceiver reset watchdog 2021-10-17 20:19:04 -07:00
Alex Forencich
7594ac0775 Init and reset to same value 2021-10-17 02:13:14 -07:00
Alex Forencich
45ddd70036 merged changes in axis 2021-10-17 01:42:17 -07:00
Alex Forencich
2cd70281ea Properly zero synchronized pointer on one-sided reset 2021-10-17 01:23:02 -07:00
Alex Forencich
9d4d8508ae Unconditionally pass through ordered set data to simplify decode logic 2021-10-16 01:25:48 -07:00
Alex Forencich
247aeae845 Detect bad XGMII encodings in PHY TX 2021-10-16 00:50:48 -07:00
Alex Forencich
3b2e6874d8 Rework XGMII to BASE-R encoder implementation 2021-10-16 00:48:01 -07:00
Alex Forencich
9667ef1f9c Detect sequence errors 2021-10-16 00:03:35 -07:00
Alex Forencich
5258bdc312 Improve bad block detection 2021-10-15 23:58:35 -07:00
Alex Forencich
571394f99f Translate LPI control characters 2021-10-15 23:53:53 -07:00
Alex Forencich
5494f3b678 Rewrite resets 2021-10-15 23:33:35 -07:00
Alex Forencich
a540e50e1c Fix XGMII to BASE-R control character mapping 2021-10-15 16:14:02 -07:00