177 Commits

Author	SHA1	Message	Date
Alex Forencich	ddd7e639da	Add tdest register to scheduler blocks	2021-12-31 17:02:59 -08:00
Alex Forencich	335a5e890b	Initial implementation of shared interface datapath	2021-12-31 14:33:31 -08:00
Alex Forencich	ce21774f06	Register space reorganization	2021-12-29 22:31:46 -08:00
Alex Forencich	6163efa0b8	Add output pipeline stage to descriptor FIFOs	2021-12-29 14:30:05 -08:00
Ulrich Langenbach	0560f98e79	support more than 4k queues (workaround quartus loop iteration limit)	2021-12-16 12:09:39 -08:00
Alex Forencich	7a43618e3c	Use start_soon instead of fork	2021-12-10 20:43:21 -08:00
Alex Forencich	7e3d8606fc	Rework window creation	2021-12-02 16:46:56 -08:00
Alex Forencich	540e7eb1de	Fix offset	2021-12-02 16:46:35 -08:00
Alex Forencich	089c405c4f	Fix clock connections	2021-11-30 16:39:27 -08:00
Alex Forencich	720a06ca8b	Update mux instances	2021-11-30 15:36:24 -08:00
Alex Forencich	ebd80e7267	Test multiple ports	2021-11-30 14:12:34 -08:00
Alex Forencich	9d817af8d1	Test all interfaces	2021-11-30 00:57:41 -08:00
Alex Forencich	639117e53f	Adjust clock connections to improve connection to testbench	2021-11-30 00:16:47 -08:00
Alex Forencich	8f887005e5	Update Ethernet interface configuration detection in testbenches	2021-11-22 17:04:50 -08:00
Alex Forencich	2aa9158d5c	Limit scheduler pipeline to a single AXI lite operation	2021-11-19 16:29:16 -08:00
Alex Forencich	74f4c6fc2d	Support using separate clock for PTP timestamps on RX path	2021-11-18 23:56:51 -08:00
Alex Forencich	c2d2b441fb	Add missing symlink	2021-11-17 18:29:26 -08:00
Alex Forencich	605965fec9	Add mqnic core logic module for AXI	2021-11-17 18:16:40 -08:00
Alex Forencich	5bf9de656c	Update testbenches	2021-11-17 18:08:40 -08:00
Alex Forencich	bd8a0513ed	Add mqnic core logic for Stratix 10 GX/SX/TX/MX	2021-11-07 13:28:12 -08:00
Alex Forencich	7ab18f8602	Increase event FIFO depth	2021-11-06 16:14:49 -07:00
Alex Forencich	fb0f6f67f7	Remove debug code	2021-11-06 16:14:32 -07:00
Alex Forencich	f8a24d1c46	Add attributes to RAMs for proper synthesis in Quartus	2021-11-06 16:14:22 -07:00
Alex Forencich	aa89471cca	Add bus_num port to mqnic_core_pcie	2021-11-03 21:40:19 -07:00
Alex Forencich	7ac4797336	Add default_nettype none and resetall directives	2021-10-20 21:53:39 -07:00
Alex Forencich	607257d7bb	Fix connections	2021-10-20 20:43:11 -07:00
Alex Forencich	2c038c9b7b	Update FIFO instance	2021-10-13 16:44:05 -07:00
Alex Forencich	620791e562	Add TDMA testbench	2021-09-13 17:11:39 -07:00
Alex Forencich	ec89492d24	Fix control register addressing bug	2021-09-11 00:49:48 -07:00
Alex Forencich	d24c53a2ad	Add application section	2021-09-09 16:01:26 -07:00
Alex Forencich	371717b854	Add block names	2021-09-09 14:12:41 -07:00
Alex Forencich	97e3daa36c	Extract information from design instead of env vars	2021-09-08 16:44:58 -07:00
Alex Forencich	c920272e84	Use interface address widths directly instead of BAR size parameters	2021-09-08 14:51:18 -07:00
Alex Forencich	cef144e376	Expose DMA_LEN_WIDTH and DMA_TAG_WIDTH parameters	2021-09-08 00:18:11 -07:00
Alex Forencich	c00a53155d	Fix alignment	2021-09-07 01:38:09 -07:00
Alex Forencich	bdd2312ecc	More descriptive parameter and signal names for AXI lite control connections	2021-09-07 01:35:15 -07:00
Alex Forencich	8cf16c182b	More descriptive parameter names (SYNC instead of INT)	2021-09-07 01:29:35 -07:00
Alex Forencich	15dec9458a	Add statistics counter subsystem	2021-09-05 23:03:22 -07:00
Alex Forencich	9ccd43d470	Add statistics collection modules	2021-09-05 18:28:37 -07:00
Alex Forencich	5d760851ac	Limit queue manager pipelines to a single AXI lite operation	2021-09-05 12:46:56 -07:00
Alex Forencich	ef00d5ccfd	Add parameters for FIFO output pipeline register depth	2021-09-02 14:45:18 -07:00
Alex Forencich	f3eeb653d1	Fix test	2021-09-02 00:00:37 -07:00
Alex Forencich	de869347cd	Register interrupt signal	2021-09-01 13:14:02 -07:00
Alex Forencich	df9523011c	Normalize instance names	2021-09-01 02:14:53 -07:00
Alex Forencich	37a558e4f6	Add pipeline FIFOs	2021-08-31 22:30:45 -07:00
Alex Forencich	915a915d6e	Enable PCIe flow control in core tests	2021-08-31 20:38:08 -07:00
Alex Forencich	a5519cd607	Default to US+ configuration	2021-08-31 18:57:32 -07:00
Alex Forencich	bdbdc11841	Initial commit of core logic	2021-08-31 18:42:19 -07:00
Alex Forencich	9731ea5188	Add new PTP subsystem	2021-08-31 01:39:19 -07:00
Alex Forencich	cef2602efe	Reorganize address space to place port registers in interface register space	2021-08-30 01:29:25 -07:00