70 Commits

Author	SHA1	Message	Date
Alex Forencich	335a5e890b	Initial implementation of shared interface datapath	2021-12-31 14:33:31 -08:00
Alex Forencich	ce21774f06	Register space reorganization	2021-12-29 22:31:46 -08:00
Alex Forencich	7a43618e3c	Use start_soon instead of fork	2021-12-10 20:43:21 -08:00
Alex Forencich	7e3d8606fc	Rework window creation	2021-12-02 16:46:56 -08:00
Alex Forencich	ebd80e7267	Test multiple ports	2021-11-30 14:12:34 -08:00
Alex Forencich	9d817af8d1	Test all interfaces	2021-11-30 00:57:41 -08:00
Alex Forencich	639117e53f	Adjust clock connections to improve connection to testbench	2021-11-30 00:16:47 -08:00
Alex Forencich	8f887005e5	Update Ethernet interface configuration detection in testbenches	2021-11-22 17:04:50 -08:00
Alex Forencich	74f4c6fc2d	Support using separate clock for PTP timestamps on RX path	2021-11-18 23:56:51 -08:00
Alex Forencich	c2d2b441fb	Add missing symlink	2021-11-17 18:29:26 -08:00
Alex Forencich	605965fec9	Add mqnic core logic module for AXI	2021-11-17 18:16:40 -08:00
Alex Forencich	5bf9de656c	Update testbenches	2021-11-17 18:08:40 -08:00
Alex Forencich	bd8a0513ed	Add mqnic core logic for Stratix 10 GX/SX/TX/MX	2021-11-07 13:28:12 -08:00
Alex Forencich	620791e562	Add TDMA testbench	2021-09-13 17:11:39 -07:00
Alex Forencich	d24c53a2ad	Add application section	2021-09-09 16:01:26 -07:00
Alex Forencich	97e3daa36c	Extract information from design instead of env vars	2021-09-08 16:44:58 -07:00
Alex Forencich	c920272e84	Use interface address widths directly instead of BAR size parameters	2021-09-08 14:51:18 -07:00
Alex Forencich	cef144e376	Expose DMA_LEN_WIDTH and DMA_TAG_WIDTH parameters	2021-09-08 00:18:11 -07:00
Alex Forencich	8cf16c182b	More descriptive parameter names (SYNC instead of INT)	2021-09-07 01:29:35 -07:00
Alex Forencich	15dec9458a	Add statistics counter subsystem	2021-09-05 23:03:22 -07:00
Alex Forencich	9ccd43d470	Add statistics collection modules	2021-09-05 18:28:37 -07:00
Alex Forencich	ef00d5ccfd	Add parameters for FIFO output pipeline register depth	2021-09-02 14:45:18 -07:00
Alex Forencich	f3eeb653d1	Fix test	2021-09-02 00:00:37 -07:00
Alex Forencich	37a558e4f6	Add pipeline FIFOs	2021-08-31 22:30:45 -07:00
Alex Forencich	915a915d6e	Enable PCIe flow control in core tests	2021-08-31 20:38:08 -07:00
Alex Forencich	bdbdc11841	Initial commit of core logic	2021-08-31 18:42:19 -07:00
Alex Forencich	c926fd2ca1	Remove extraneous imports	2021-06-28 22:35:22 -07:00
minseongg	9af504a6c0	Update cmac_pad testbench	2021-06-28 22:33:57 -07:00
minseongg	8db2faddc6	Update cmac_pad testbench	2021-06-28 22:33:57 -07:00
minseongg	dc5c8232f9	Add cmac_pad testbench	2021-06-28 22:33:57 -07:00
Alex Forencich	32abea89fa	Update testbenches	2021-03-06 20:30:25 -08:00
Alex Forencich	c0c2f933c0	Rework sim_build output directory, fix default makefile target	2020-12-29 17:28:53 -08:00
Alex Forencich	0c0fdc479b	Update testbenches for async send/recv	2020-12-18 17:40:36 -08:00
Alex Forencich	b5ee772761	Migrate test infrastructure to cocotb	2020-12-15 16:52:20 -08:00
Alex Forencich	a37d9b3465	New transceiver control reigster definitions	2020-09-19 17:25:58 -07:00
Alex Forencich	3284ec3848	New I2C register definitions	2020-09-19 17:25:58 -07:00
Alex Forencich	495178e1dc	Fix mask	2020-07-28 18:30:52 -07:00
Alex Forencich	4e958096b2	Update driver model to set MTU registers	2020-05-01 19:19:56 -07:00
Alex Forencich	8b535e54ac	Add MTU registers	2020-05-01 18:55:01 -07:00
Alex Forencich	1f76606667	Move TDMA registers	2020-05-01 16:55:57 -07:00
Alex Forencich	9e64d19ea5	Use scatter descriptor blocks in driver model	2020-04-21 01:04:07 -07:00
Alex Forencich	2c6e9673f7	Add log_desc_block_size ring parameter in driver model	2020-04-21 00:58:12 -07:00
Alex Forencich	d0cf549057	Add log desc block size field to queue manager	2020-04-20 20:45:10 -07:00
Alex Forencich	50af74aa88	Change QUEUE_LOG_SIZE_WIDTH to LOG_QUEUE_SIZE_WIDTH	2020-04-20 18:43:26 -07:00
Alex Forencich	a196cd227c	Enable bus mastering and MSI in driver model	2020-03-12 15:32:08 -07:00
Alex Forencich	457f4d7f3f	Use configured ring stride	2020-03-12 15:28:00 -07:00
Alex Forencich	0c32192226	Use constants instead of magic numbers	2020-03-12 15:08:20 -07:00
Alex Forencich	1216f7a76e	Offset packet start by 10 bytes to match Linux kernel skb alignment	2020-03-08 21:56:08 -07:00
Alex Forencich	4dd5104f4d	Stripe completion queues across event queues	2020-03-06 00:58:30 -08:00
Alex Forencich	58200e9851	Fix testbench	2019-12-28 01:15:40 -08:00