15 Commits

Author	SHA1	Message	Date
Alex Forencich	5e12f97518	MAC optimizations	2018-10-19 15:24:33 -07:00
Alex Forencich	25d1b373cc	Use don't care bits	2018-06-14 15:20:20 -07:00
Alex Forencich	0fd157964a	Happy new year	2018-02-26 12:50:51 -08:00
Alex Forencich	9a507b388d	Update LFSR module	2017-06-09 21:17:28 -07:00
Alex Forencich	9b2ac9dfc1	Happy new year	2017-05-18 13:47:45 -07:00
Alex Forencich	47ca9a8725	Replace eth_crc modules for generic lfsr module	2016-06-28 17:31:58 -07:00
Alex Forencich	9c01e114b4	Happy new year	2016-01-05 00:34:32 -08:00
Alex Forencich	a98dfce099	Update output registers, remove extraneous resets, fix constant widths	2015-11-09 23:50:34 -08:00
Alex Forencich	17bf03d7a2	10G MAC RX optimizations	2015-11-03 15:30:08 -08:00
Alex Forencich	cc5fead04d	Convert to synchronous resets	2015-10-09 22:36:58 -07:00
Alex Forencich	4156d8511a	Rework CRC check	2015-08-07 12:13:44 -07:00
Alex Forencich	abe0d926ba	Consider any control characters in packet body as errors	2015-06-23 08:55:39 -07:00
Alex Forencich	455ddf5df2	Fix error detect in 10G MAC	2015-06-06 00:49:40 -07:00
Alex Forencich	0352d55084	Add default case	2015-05-16 22:34:29 -07:00
Alex Forencich	bf349b16ba	Add 10G MAC module	2015-05-08 00:05:21 -07:00