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2,396 Commits 1 Branch 0 Tags
Commit Graph

16 Commits

Author SHA1 Message Date
Alex Forencich
3997e0d95b Parametriztion updates, add RAM_ADDR_WIDTH as a top-level parameter 2022-02-15 18:01:43 -08:00
Alex Forencich
137a6778da Combine interface control blocks 2022-01-15 21:53:13 -08:00
Alex Forencich
335a5e890b Initial implementation of shared interface datapath 2021-12-31 14:33:31 -08:00
Alex Forencich
ce21774f06 Register space reorganization 2021-12-29 22:31:46 -08:00
Alex Forencich
540e7eb1de Fix offset 2021-12-02 16:46:35 -08:00
Alex Forencich
7ab18f8602 Increase event FIFO depth 2021-11-06 16:14:49 -07:00
Alex Forencich
7ac4797336 Add default_nettype none and resetall directives 2021-10-20 21:53:39 -07:00
Alex Forencich
de869347cd Register interrupt signal 2021-09-01 13:14:02 -07:00
Alex Forencich
cef2602efe Reorganize address space to place port registers in interface register space 2021-08-30 01:29:25 -07:00
Alex Forencich
d46cb16dbf Add scheduler block 2021-08-30 01:28:55 -07:00
Alex Forencich
34150323df Remove obsolete packet table size parameters 2021-08-20 18:15:06 -07:00
Alex Forencich
a19474f9dd Use AXI lite crossbar 2021-08-11 01:31:34 -07:00
Alex Forencich
e0e34a9f0d Update designs for PCIe module changes 2021-08-02 23:04:52 -07:00
Alex Forencich
0a7f1ccbbe Remove string parameters 2021-06-02 18:18:23 -07:00
Alex Forencich
a3c104f7dd Connect write done signals 2021-02-24 15:07:26 -08:00
Alex Forencich
91edbbf3dc Rename port and interface modules 2020-11-26 15:05:59 -08:00