81 Commits

Author	SHA1	Message	Date
Alex Forencich	32abea89fa	Update testbenches	2021-03-06 20:30:25 -08:00
Alex Forencich	d416e9f7fa	Roll back PCIe tag count to 64	2021-03-05 14:04:52 -08:00
Alex Forencich	a644d6dd3f	Update Vivado makefiles	2021-03-01 23:05:37 -08:00
Alex Forencich	d0b19efce5	Reconcile PCIe changes	2021-03-01 00:25:15 -08:00
Alex Forencich	a3c104f7dd	Connect write done signals	2021-02-24 15:07:26 -08:00
Alex Forencich	2779087de9	Constrain DMA muxes to same SLR	2021-02-23 02:17:10 -08:00
Alex Forencich	ceebb9f20e	Add more PCIe-related components to PCIe pblock	2021-02-23 00:55:05 -08:00
Alex Forencich	1d7dc703b5	Add cfgmclk timing constraints, rework reset connections	2021-02-05 18:00:56 -08:00
Alex Forencich	b16fe8f7e7	More XDC clean up, add IO delay constraints for low speed IO	2021-02-05 16:08:23 -08:00
Alex Forencich	89d7042aeb	Add CMS IP to all Alveo designs	2021-01-31 14:17:49 -08:00
Alex Forencich	722bd929b8	Placement updates	2021-01-31 12:48:49 -08:00
Alex Forencich	151ed7e179	Add extra reset registers	2021-01-31 11:10:03 -08:00
Alex Forencich	1248ca1a2e	Add power budget to Alveo XDC files	2021-01-29 15:44:15 -08:00
Alex Forencich	972e41e433	Update placement constraints	2021-01-14 22:06:24 -08:00
Alex Forencich	6476ad3fd0	Separate file for placement constraints	2021-01-14 14:42:58 -08:00
Alex Forencich	9accebffb9	Add pipeline registers, floorplanning constraints for AU200 100G design	2021-01-13 22:56:10 -08:00
Alex Forencich	9d97bf5a70	Add placement constraints for AU200 10G design	2021-01-13 22:14:18 -08:00
Alex Forencich	c0c2f933c0	Rework sim_build output directory, fix default makefile target	2020-12-29 17:28:53 -08:00
Alex Forencich	0c0fdc479b	Update testbenches for async send/recv	2020-12-18 17:40:36 -08:00
Alex Forencich	b5ee772761	Migrate test infrastructure to cocotb	2020-12-15 16:52:20 -08:00
Alex Forencich	91edbbf3dc	Rename port and interface modules	2020-11-26 15:05:59 -08:00
Alex Forencich	53f4275ea2	Add output registers for I2C interface to improve timing	2020-10-13 23:52:52 -07:00
Alex Forencich	ac4859d88e	Fix user_clk_frequency setting in testbenches	2020-10-12 23:07:43 -07:00
Alex Forencich	d6810db7f5	Add extra output register for flash interface to improve routability and timing	2020-10-08 19:22:28 -07:00
Alex Forencich	b57905eed6	Fix flash IDs	2020-10-02 20:30:05 -07:00
Alex Forencich	9dbac6d446	Add QSPI flash access and IPROG for Alveo	2020-09-29 21:12:05 -07:00
Alex Forencich	1806a464bb	Update flash programming commands	2020-09-29 18:31:10 -07:00
Alex Forencich	5ddca32315	Fix flash settings	2020-09-29 17:32:06 -07:00
Alex Forencich	96f015d905	Update LED connections	2020-09-29 00:38:04 -07:00
Alex Forencich	5ddff9d17e	Add 100G mqnic design for Alveo U200	2020-09-22 01:01:07 -07:00
Alex Forencich	6f72ac05b7	Add 10G mqnic design for Alveo U200	2020-09-22 01:00:23 -07:00