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4 Commits

Author SHA1 Message Date
Alex Forencich
dfae34ed25 Pass through PTP pipelining settings 2022-03-28 00:50:29 -07:00
Alex Forencich
e95c132045 Route PCIe user reset through BUFG 2022-03-25 01:26:29 -07:00
Alex Forencich
1291d7b1b7 Add pipeline registers to TDMA BER modules 2022-03-15 17:40:27 -07:00
Alex Forencich
2024ac60ec Unified 10G/25G design for AU280 2022-03-14 21:37:40 -07:00